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Part: 74ALVC162334
Category:
Logic
Description: 3.3V CMOS 16-BIT Universal Bus Driver With 3-STATE Outputs
Company: Integrated Device Technology, Inc.
Datasheet: Download 74ALVC162334 datasheet File size : 67 kB
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Datasheet text preview:
IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC162334
FEATURES:
DESCRIPTION:
This 16-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC162334 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels.
DRIVE FEATURES:
· Balanced Output Drivers: ±12mA · Low Switching Noise
APPLICATIONS:
· SDRAM Modules · PC Motherboards · Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
1
C LK
48
LE
25
A1
47
1D
2
Y1
C1 C LK
T O 15 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4687/2
IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 GND Y7 Y8 Y9 Y 10 GND Y 11 Y 12 VCC Y13 Y 14 GND Y 15 Y 16 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CLK A1 A2 GND A3 A4 V CC A5 A6 GND A7 A8 A9 A10 GND A11 A12 V CC A 13 A 14 GND A 15 A 16 LE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ±50 50 ±100
Unit V V °C mA mA mA mA
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CO U T Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1 . As applicable to the device type.
FUNCTION TABLE(1)
Inputs OE H L L L L L LE X L L H H H CLK X X X L or H Ax X L H L H X Outputs Yx Z L H L H Y0
(2)
SSOP/ TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names OE CLK LE Ax Yx Description 3-State Output Enable Inputs (Active LOW) Register Input Clock Latch Enable (Active LOW) Data Inputs 3-State Outputs
NOTE: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2 . Output level before the indicated steady-state input conditions were established.
2
IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
3
IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 31 7 VCC = 3.3V ± 0.3V Typical 36 11 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW tW tSU tSU tSU tH tH tSK(O) Propagation Delay Ax to Yx Propagation Delay LE to Yx Propagation Delay CLK toYx Output Enable Time OE to Yx Output Disable Time OE to Yx Pulse Duration, LE LOW Pulse Duration, CLK HIGH or LOW Set-up Time, data before CLK Set-up Time, data before LE, CLK HIGH Set-up Time, data before LE, CLK LOW Hold Time, data after CLK Hold Time, data after LE, CLK HIGH or LOW Output Skew(2) 3.3 3.3 1.4 1.2 1.4 0.9 1.1 -- -- -- -- -- -- -- -- -- 3.3 3.3 1.7 1.6 1.5 0.9 1.1 -- -- -- -- -- -- -- -- -- 3.3 3.3 1.5 1.3 1.2 0.9 1.1 -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ps 1 4.7 -- 5.1 1.7 5 ns 1 6.4 -- 6.4 1.1 5.4 ns 1 5.2 -- 5.4 1 4.9 ns 1 5.8 -- 6 1.3 5 ns Parameter Min. 150 1 Max. -- 4.4 VCC = 2.7V Min. 150 -- Max. -- 4.5 VCC = 3.3V ± 0.3V Min. 150 1.1 Max. -- 3.6 Unit MHz ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 . Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V IH VT 0V VOH VT VOL V IH VT 0V
A L V C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 P u ls e G e n e ra to r
( 1 , 2)
S A M E PHASE I N P U T TRAN S I T I O N
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
V LOAD O pen GND
tP L H O U TPU T tP L H O P P O S I T E PHASE I N P U T TRAN S I T I O N
tP H L
6 2.7 1.5 300 300 50
tP H L
Propagation Delay
EN AB LE C O N TR O L IN P U T tP Z L
D IS A B L E
V IN D .U . T .
V OUT
V IH VT 0V V L O A D /2 V O L + VLZ VOL VOH V O H - VHZ 0V
A L V C Link
tP L Z V L O A D /2 VT tP H Z VT 0V
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
O U TPU T S W IT C H N O R M ALLY CLO SED LO W tP Z H O U TPU T S W IT C H N O R M ALLY OPEN H IG H
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
A L V C Link
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
V IH IN P U T VT 0V V OH OUTPUT 1 VT V OL V OH OUTPUT 2 tP L H 2 tP H L 2
A L V C Link
DATA IN P U T T IM IN G IN P U T A SYNC HRO N OU S C O N TR O L SYNC HRO N OU S C O N TR O L
tS U
tH
tR E M
tS U
tH
Set-up, Hold, and Release Times
tP L H 1
tP H L 1
L O W - H IG H - L O W PU LS E tW H IG H -L O W -H IG H PU LS E
VT
tS K (x)
t S K (x)
VT
A L V C Link
VT V OL
Pulse Width
t S K ( x ) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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