|
|
Part: 74ALVC16244A
Category:
Logic
Description: 3.3V CMOS 16-BIT Buffer/driver With 3-STATE Outputs
Company: Integrated Device Technology, Inc.
Datasheet: Download 74ALVC16244A datasheet File size : 67 kB
Request For quote: Find where to buy 74ALVC16244A
Datasheet text preview:
IDT74ALVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
FEATURES: DESCRIPTION:
IDT74ALVC16244A
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in SSOP, TSSOP, and TVSOP packages
This 16-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVC16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. The ALVC16244A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
DRIVE FEATURES:
· High Output Drivers: ±24mA · Suitable for heavy loads
APPLICATIONS:
· 3.3V high speed systems · 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1OE 1 3O E 25
1A 1
47
2
1Y 1
3A 1
36
13
3Y 1
1A 2
46
3
1Y 2
3A 2
35
14
3Y 2
1A 3
44
5
1Y 3
3A 3
33
16
3Y 3
1A 4
43
6
1Y 4
3A 4
32
17
3Y 4
2OE
48
4O E
24
2A 1
41
8
2Y 1
4A 1
30
19
4Y 1
2A 2
40
9
2Y 2
4A 2
29
20
4Y 2
2A 3
38
11
2Y 3
4A 3
27
22
4Y 3
2A 4
37
12
2Y 4
4A 4
26
23
4Y 4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4698/1
IDT74ALVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1O E 1Y 1 1Y 2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ±50 50 ±100
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2O E 1A 1 1A 2
Unit V V °C mA mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
1Y 3 1Y 4
GND
1A 3 1A 4
V CC
2Y 1 2Y 2
VCC
2A 1 2A 2
GND
2Y 3 2Y 4 3Y 1 3Y 2
GND
2A 3 2A 4 3A 1 3A 2
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CO U T Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
3Y 3 3Y 4
GND
3A 3 3A 4
NOTE: 1 . As applicable to the device type.
V CC
4Y 1 4Y 2
VCC
4A 1 4A 2
PIN DESCRIPTION
Pin Names xOE xAx xYx Data Inputs 3-State Outputs Description 3-State Output Enable Inputs (Active LOW)
GND
4Y 3 4Y 4 4O E
GND
4A 3 4A 4 3O E
SSOP/ TSSOP/ TVSOP TOP VIEW
FUNCTION TABLE(1)
Inputs xOE L L H
NOTE: 1 . H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High-Impedance
Outputs xAx H L X xYx H L Z
2
IDT74ALVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
3
IDT74ALVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 16 4 VCC = 3.3V ± 0.3V Typical 19 5 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xA to xBx Output Enable Time OE to xBx Output Disable Time OE to xBx Output Skew(2) -- -- -- -- -- 500 ps 1 5.8 -- 5.2 1 5 ns 1 6.3 -- 6 1 5 ns Min. 1 Max. 4.4 -- VCC = 2.7V Min. Max. 4 VCC = 3.3V ± 0.3V Min. 1 Max. 3.6 Unit ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 . Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVC16244A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V IH VT 0V VOH VT VOL V IH VT 0V
A L V C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 P u ls e G e n e ra to r
( 1 , 2)
S A M E PHASE I N P U T TRAN S I T I O N
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
V LOAD O pen GND
tP L H O U TPU T tP L H O P P O S I T E PHASE I N P U T TRAN S I T I O N
tP H L
6 2.7 1.5 300 300 50
tP H L
Propagation Delay
EN AB LE C O N TR O L IN P U T tP Z L
D IS A B L E
V IN D .U . T .
V OUT
V IH VT 0V V L O A D /2 V O L + VLZ VOL VOH V O H - VHZ 0V
A L V C Link
tP L Z V L O A D /2 VT tP H Z VT 0V
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
O U TPU T S W IT C H N O R M ALLY CLO SED LO W tP Z H O U TPU T S W IT C H N O R M ALLY OPEN H IG H
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
A L V C Link
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
V IH IN P U T VT 0V V OH OUTPUT 1 VT V OL V OH OUTPUT 2 tP L H 2 tP H L 2
A L V C Link
DATA IN P U T T IM IN G IN P U T A SYNC HRO N OU S C O N TR O L SYNC HRO N OU S C O N TR O L
tS U
tH
tR E M
tS U
tH
Set-up, Hold, and Release Times
tP L H 1
tP H L 1
L O W - H IG H - L O W PU LS E tW H IG H -L O W -H IG H PU LS E
VT
tS K (x)
t S K (x)
VT
A L V C Link
VT V OL
Pulse Width
t S K ( x ) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
