Details, datasheet, quote on part number: 74ALVC16836
Description3.3V CMOS 20-BIT Universal Bus Driver With 3-STATE Outputs
CompanyIntegrated Device Technology, Inc.
DatasheetDownload 74ALVC16836 datasheet


Features, Applications

0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC 0.3V, Normal Range VCC to 3.6V, Extended Range VCC 0.2V CMOS power levels (0.4 W typ. static) Rail-to-Rail output swing for increased noise margin Available in SSOP, TSSOP, and TVSOP packages

This 20-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. LE is high, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC16836 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

High Output Drivers: 24mA Suitable for heavy loads
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Symbol Description Max VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI > VCC Continuous Clamp Current, < 0 Continuous Current through each VCC or GND 50 to

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.

Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 Max. 7 9 Unit pF

Pin Names OE CLK Yx NC Description 3-State Output Enable Inputs (Active LOW) Register Input Clock Latch Enable (Active LOW) Data Inputs 3-State Outputs No Internal Connection 2

NOTES: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established.

Following Conditions Apply Unless Otherwise Specified: Operating Condition: to +85C

Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC to 2.7V VCC to 3.6V VCC to 2.7V VCC to 3.6V VCC = 3.6V VCC = 3.6V VCC VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 100 0.1 Max. A V Unit V

Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC to 3.6V IOH 0.1mA IOH 6mA IOH 12mA Min. VCC Max. V Unit V

NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. + 85C.


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