· 0.5 MICRON CMOS Technology· Typical tSK(o) (Output Skew) < 250ps· ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0)· VCC ± 0.3V, Normal Range· VCC to 3.6V, Extended Range· VCC ± 0.2V· CMOS power levels (0.4µ W typ. static)· Rail-to-Rail output swing for increased noise margin· Available in SSOP, TSSOP, and TVSOP packages

This multiplexed D-type latch is built using advanced dual metal CMOS technology. The ALVCH162260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications. Three 12-bit I/O ports (A1­A12, 1B1­1B12, and 2B1­2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVCH162260 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The "A" port has ± 24mA driver. The ALVCH162260 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI > VCC Continuous Clamp Current, < 0 Continuous Current through each VCC or GND Max ­50 to Unit °C mA

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.

Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 Max. 7 9 Unit pF

NOTES: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2. Output level before the indicated steady-state input conditions were established.

Pin Names LE1B LE2B SEL OEA OE1B OE2B I/O Description Bidirectional Data Port A. Usually connected to the CPU's address/data bus.

Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.

Latch Enable Input for A-1B Latch. The latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B Latch. The latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for 1B-A Latch. The latch is open when LE1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LE1B. Latch Enable Input for 2B-A Latch. The latch is open when LE2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition or 2B Port Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW) Output Enable for 1B Port (Active LOW) Output Enable for 2B Port (Active LOW)