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Details, datasheet, quote on part number:74ALVCH162268
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Datasheet text preview:
IDT74ALVCH162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH162268
DESCRIPTION:
This 12-bit to 24-bit registered bus exchanger is built using advanced dual metal CMOS technology. This device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lowerfrequency bus. The ALVCH162268 device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the lowto-high transition of the clock (CLK) input when the appropriate clockenable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). These control terminals are registered to synchronize the busdirection changes with CLK. The ALVCH162268 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The "A" port has a ±24mA driver. The ALVCH162268 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
· High Output Drivers: ±24mA (A port) · Balanced Output Drivers: ±12mA (B port)
APPLICATIONS:
· 3.3V high speed systems · 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
CLK
29 2
C LKE N 1B
27
C LKE N 2B
30
C LKE N A 1
C LKE N A 2 OEB
55
C1
56
1D C1
S EL OEA
28
1D
1
1D C1
CE C1 1D
23
1B 1
A1
8
0 1
CE C1 1D
6
2B 1
CE C1 1D
CE C1 1D
CE C1 1D 1 of 12 Channels
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4535/1
IDT74ALVCH162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA C LKEN 1B
2B 3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ± 50 50 ±100 Unit V V °C mA mA mA mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OEB C LKEN A2
2B 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
2B 2 2B 1
GND
2B 5 2B 6
VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A 10 A 11 A 12 VCC
1B 1 1B 2
VCC
2B 7 2B 8 2B 9
GND
2B 10 2B 1 1 2B 1 2 1B 1 2 1B 1 1 1B 1 0
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
1B 9 1B 8 1B 7
NOTE: 1 . As applicable to the device type.
FUNCTION TABLES(1)
OUTPUT ENABLE
Inputs CLK OEA H H L L OEB H L H L Ax Z Z Active Active Outputs 1Bx, 2Bx Z Active Z Active
VCC
1B 6 1B 5
GND
1B 3
GND
1B 4
C LKEN 2B SEL
C LKEN A1 C LK
SSOP/ TSSOP/ TVSOP TOP VIEW CLKENA1 H L L X X
A-TO-B STORAGE (OEB = L AND OEA = H)
Inputs CLKENA2 H L L L L CLK X Ax X L H L H Outputs 1Bx
(2) 1B0
2Bx 2B0 L H L H
(2)
L
(3) (3)
H
X X
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IDT74ALVCH162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES (CONTINUED)(1)
B-TO-A STORAGE (OEA = L AND OEA = H)
Inputs CLKEN1B H X L L X X CLKEN2B X H X X L L CLK X X SEL H L H H L L 1Bx X X L H X X 2Bx X X X X L H Output Ax A0 A0
(2) (2)
L H L H
NOTE: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2 . Output level before the indicated steady-state input conditions were established. 3 . Two CLK edges are needed to propagate data.
PIN DESCRIPTION
Pin Names Ax (1:12) 1Bx (1:12) 2Bx (1:12) CLK CLKENA1 CLKENA2 CLKEN1B CLKEN2B SEL OEA OEB I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's address/data bus.
(1) (1)
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory. Clock Input
(1)
Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-1B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the A-1B Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the A-1B Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port (Active LOW). Synchronous Output Enable for A Port (Active LOW) Synchronous Output Enable for A Port (Active LOW)
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCH162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
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IDT74ALVCH162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 87 80 VCC = 3.3V ± 0.3V Typical 120 118 Unit pF
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