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Details, datasheet, quote on part number:74ALVCH162373
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Datasheet text preview:
IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH162373
DESCRIPTION:
This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be enetered while the outputs are in the high-impedance state. The ALVCH162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162373 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
· Balanced Output Drivers: ±12mA · Low switching noise
APPLICATIONS:
· 3.3V high speed systems · 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1O E
1
2O E
24
1LE
48
2L E
25
C1
2
C1
1Q 1 2D 1
36 13
2Q 1
1D 1
47
1D
1D
T O 7 OTHER CHANNELS
T O 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4575/2
IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1LE 1D 1 1D 2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ± 50 50 ±100 Unit V V °C mA mA mA mA
1O E 1Q 1 1Q 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND
1Q 3 1Q 4
GND
1D 3 1D 4
V CC
1Q 5 1Q 6
V CC
1D 5 1D 6
GND
1Q 7 1Q 8 2Q 1 2Q 2
GND
1D 7 1D 8 2D 1 2D 2
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
2Q 3 2Q 4
GND
2D 3 2D 4
NOTE: 1 . As applicable to the device type.
VCC
2Q 5 2Q 6
V CC
2D 5 2D 6
PIN DESCRIPTION
Pin Names xDx xLE xQx xOE Description Data Inputs(1) Latch Enable Inputs 3-State Outputs 3-State Output Enable Input (Active LOW)
GND
2Q 7 2Q 8 2O E
GND
2D 7 2D 8 2LE
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP/ TVSOP TOP VIEW
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
Inputs xOE L L H L xLE H H X L xDx H L X X Outputs xQx H L Z Qo(2)
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2 . Output level before the indicated steady-state input conditions were established.
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IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
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IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 19 4 VCC = 3.3V ± 0.3V Typical 22 5 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(O) Parameter Propagation Delay xDx to xQx Propagation Delay xLE to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Setup Time, data before LE Hold Time, data after LE Pulse Duration, LE HIGH or LOW Output Skew(2) 2 1.5 3.3 -- -- -- -- -- 2 1.5 3.3 -- -- -- -- -- 2 1.5 3.3 -- -- -- -- 500 ns ns ns ps 1.5 5.6 1.5 5.5 1.5 4.5 ns 1.5 6.5 1.5 6 1.5 5 ns 2 5.6 2 5 2 4 ns Min. 1.5 Max. 5.3 VCC = 2.7V Min. 1.5 Max. 4.5 VCC = 3.3V ± 0.3V Min. 1.5 Max. 4 Unit ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 . Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V IH VT 0V VOH VT VOL V IH VT 0V
A L V C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 P u lse G e n erato r
(1 , 2)
S A M E PHASE IN P U T TRANSITION
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
V LOAD Open GND
tP L H O U TPU T tP L H O P P O S IT E PHASE IN P U T TRANSITION
tP H L
6 2.7 1.5 300 300 50
tP H L
Propagation Delay
ENA BLE CONTROL IN P U T tP Z L O U TPU T S W IT C H N O R M A LL Y CLO SED LO W tP Z H O U TPU T S W IT C H N O R M A LL Y OPEN H IG H V L O A D /2 VT tP H Z VT 0V tP L Z D IS A B L E V IH VT 0V V L O A D /2 V LZ VOL VOH VHZ 0V
A L V C Link
V IN D .U .T .
V O UT
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
Enable and Disable Times
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. V IH DATA VT IN P U T 0V tS U tH V IH T IM IN G VT IN P U T 0V tR E M V IH ASYNCHRONOUS VT C O N TR O L 0V V IH SYN CHRONOUS VT C O N TR O L tS U 0V tH
A L V C Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
V IH IN P U T VT 0V VOH OUTPU T 1 VT VOL VOH OUTPU T 2 tP L H 2 tP H L 2
A L V C Link
Set-up, Hold, and Release Times
tP L H 1
tP H L 1
L O W -H I G H -LO W PULSE tW H IG H -L O W -H IG H PULSE
VT
tS K (x)
tS K (x)
VT VOL
VT
A L V C Link
Pulse Width
tS K (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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