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Part: 74ALVCH32501
Category:
Logic
Description: 3.3V CMOS 36-BIT Universal Bus Transceiver With 3-STATE Outputs And Bus-hold
Company: Integrated Device Technology, Inc.
Datasheet: Download 74ALVCH32501 datasheet File size : 67 kB
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Datasheet text preview:
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in 114-ball LFBGA package
IDT74ALVCH32501
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
· High Output Drivers: ±24mA · Suitable for Heavy Loads
APPLICATIONS:
· 3.3V high speed systems · 3.3V and lower voltage computing systems
This 36-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH32501 combines D-type latches and Dtype flip-flops to allow data flow in transparent latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a HIGH or low logic level. If LEAB is low, the A bus data is stored in the latch/ flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. This ALVCH32501 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH32501 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
B3 J4 K3 J3 A4 A3
1OEAB 1CLKBA 1LEBA 1OEBA 1CLKAB 1LEAB
2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB C C D
A5
L3 V4 W3 V3 K5 K2 C C D L5
1A1
A2
1B1 2A1
D
L2
2B1
D
C D
C D
C D
C D
TO 17 OTHER CHANNELS
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2 0 0 2 Integrated Device Technology, Inc.
DECEMBER 2002
DSC-4764/2
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6 1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B15 1B17
NC
2CLKAB
2B2
2B4
2B6
2B8
2B10
2B12
2B14
2B15
2B17
5
1B1
1B3
1B5
1B7
1B9
1B11
1B13
1B16
1B18
2B1
2B3
2B5
2B7
2B9
2B11
2B13
2B16
2B18
4 1CLKAB
GND
GND VCC GND GND VCC GND
1A5 1A7 1A9
GND GND
1A11
VCC VCC
1A13
GND 1CLKBA GND
1A16 1OEBA
GND
1LEBA
GND
2OEAB
GND GND
2A3
VCC VCC
2A5
GND GND
2A7
GND GND
2A9
VCC VCC
2A11
GND 2CLKBA GND
2OEBA 2LEBA
3
1LEAB 1OEAB
GND
2A13
2
1A1
1A3
1A18
2LEAB
2A1
2A16
2A18
1
1A2 A
1A4 B
1A6 C
1A8 D
1A10 E
1A12 F
1A14 G
1A15 H
1A17 J
NC
K
2A2 L
2A4 M
2A6 N
2A8 P
2A10 R
2A12 T
2A14 U
2A15 V
2A17 W
LFBGA TOPVIEW
114 BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
5.5mm 4 5 6
16mm
2
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT IIK IOK ICC ISS Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ±50 50 ±100
Unit V V °C mA mA mA mA
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1 . As applicable to the device type.
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA xAx xBx Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs(1) B-to-A Data Inputs or A-to-B 3-State Outputs(1)
FUNCTION TABLE (EACH FLIP-FLOP)(1,2)
Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X L H xAx X L H L H X X Outputs xBx Z L H L H B(3) B(4)
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition 2 . A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 3 . Output level of Q before the indicated steady-state conditions were established. 4 . Output level of Q before the indicated steady-state conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
3
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
4
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 88 12 VCC = 3.3V ± 0.3V Typical 108 12 Unit pF
5
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