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Details, datasheet, quote on part number:74ALVCH374
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Datasheet text preview:
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
· 0.5 MICRON CMOS Technology · Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · VCC = 2.5V ± 0.2V · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · Available in QSOP, SOIC, SSOP, and TSSOP packages
IDT74ALVCH374
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
· High Output Drivers: ±24mA · Suitable for Heavy Loads
APPLICATIONS:
· 3.3V high speed systems · 3.3V and lower voltage computing systems
This octal postive edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH374 device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH374 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH374 has a "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OE
1
CLK
11
C1
1D 3 1D
2
1Q
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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© 1 9 9 9 Integrated Device Technology, Inc.
MARCH 1999
DSC-4473/1
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Max Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 50 to +50 ±50 50 ±100
Unit V V °C mA mA mA mA
OE
1Q 1D 2D 2Q 3Q 3D 4D 4Q
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC
8Q 8D 7D 7Q 6Q 6D 5D 5Q
GND
CLK
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VCC terminals. 3 . All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
QSOP/ SOIC/ SSOP/ TSSOP TOPVIEW
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1 . As applicable to the device type.
PIN DESCRIPTION
Pin Names OE CLK xD xQ Clock Input Data Inputs(1) 3-State Outputs Description 3-State Output Enable Input (Active LOW)
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE(1)
Inputs OE L L L H CLK H or L X xD H L X X Output xQ H L Q (2) Z
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition 2 . Output level of Q before the indicated steady-state conditions were established.
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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ±10 ±10 1.2 -- 40 V mV µA µA µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical VCC = 3.3V ± 0.3V Typical Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tW tSU tH tSK(O) Parameter Propagation Delay CLK to xQ Output Enable Time OE to xQ Output Disable Time OE to xQ Pulse Duration, CLK HIGH or LOW Setup Time, data before CLK Hold Time, data after CLK Output Skew(2) 3.3 2 1.5 -- -- -- -- -- 3.3 2 1.5 -- -- -- -- -- 3.3 2 1.5 -- -- -- -- 500 ns ns ns ps -- 9.5 -- 6.5 1.5 5.5 ns -- 8.5 -- 7.5 1.5 6.5 ns Min. -- Max. 8 VCC = 2.7V Min. -- Max. 7 VCC = 3.3V ± 0.3V Min. 2.2 Max. 6 Unit ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
DISABLE
VCC 500 Pulse(1, 2) Generator VIN D.U.T. RT 500 CL
ALVC Link
VLOAD Open GND VOUT CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ ENABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
Pulse Width
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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