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Part: 74ALVCHG162280
Category:
Description:
Company: Integrated Device Technology, Inc.
Datasheet: Download 74ALVCHG162280 datasheet File size : 67 kB
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IDT74ALVCHG162280 3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS, 3-STATE OUTPUTS, AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.40mm pitch TVSOP package Commercial range of 0°C to +70°C VCC = 3.3V ± 0.3V, Normal Range CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Low switching noise
IDT74ALVCHG162280
The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input. For data transfer in the B-to-A direction, the select (SEL) input selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single storage register in the 2B path. Data flow is controlled by the active-low output enable (OE) and the direction-control (DIR) inputs. The DIR control pin is registered to synchronize the bus direction changes with the clock. Two mask bits are provided for both data bytes. The data (D) outputs are controlled by OE . A port outputs have equivalent 50 series resistors. B port outputs have equivalent 20 series resistors. The switching characteristics in this spec, are based on 25pF (A Port) and 80pF (B and D Ports) loads, but production test is accomplished with the standard 50pF load. The ALVCHG162280 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
· SDRAM Modules · PC Motherboards · Workstations
DESCRIPTION:
This 16-bit to 32-bit registered bus exchanger is manufactured using advanced dual metal CMOS technology. The ALVCHG162280 is intended for use in applications in which data must be transferred from a narrow highspeed bus to a wide lower-frequency bus.
FUNCTIONAL BLOCK DIAGRAM (A and B ports)
C LK
39 40
SEL
42
OE
CE C1
41
D IR
1D
1 of 16 Channels
19
1B1
C1 A1
29
1 1D 0 C1 1D
CE C1 1D CE C1 1D CE C1 1D
18
2B1
COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
JULY 2000
DSC-4559/-
IDT74ALVCHG162280 3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (C and D Ports)
CLK
39
40
SEL
42
OE
C1
27
CE C1 1D
25
C1
1D
1D 1
CE C1 1D
24
2D 1
C1 C2
28
CE C1 1D
23
1D
1D 2
CE C1 1D
22
2D 2
2
IDT74ALVCHG162280 3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
V CC GND
2B 7 1B 7 2B 6
ABSOLUTE MAXIMUM RATINGS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 VCC GND
1B 8 2B 8 1B 9
(1)
Unit V V °C mA mA mA mA
NEW16link
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Symbol Description VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG Storage Temperature IOUT DC Output Current IIK IOK ICC ISS Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
Max. 0.5 to + 4.6 0.5 to VCC + 0.5 65 to + 150 50 to + 50 ± 50 50 ± 100
GND
1B 6 2B 5 1B 5
GND
2B 9 1B 10 2B 10
V CC
2B 4 1B 4 2B 3 1B 3
VCC
1B 11 2B 11 1B 12 2B 12
GND
2B 2 1B 2 2B 1 1B 1
GND
1B 13 2B 13 1B 14 2B 14
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
S O 8 0 -1 6 5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VCC GND
2D 2 1D 2 2D 1 1D 1
VCC GND
1B 15 2B 15 1B 16 2B 16
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol CIN CIN COUT CI/O Parameter(1) Conditions Input Capacitance VIN = 0V or Vcc Control Input Input Capacitance VIN = 0V or Vcc (C port) Output Capacitance VOUT = 0V or GND (D port) I/O Port Capacitance VOUT = 0V or GND (A or B port) Typ. Max. 4 -- 8.5 7 8.5 -- -- -- Unit pF pF pF pF
V CC C1 C2 A1 GND A2 A3 A4 VCC A5 A6 A7 GND C LK SEL
VCC A 16 A 15 A 14 GND A 13 A 12 A 11 VCC A 10 A9 A8 GND OE D IR
NOTE: 1. As applicable to the device type.
PIN DESCRIPTION
Pin Names OE CLK SEL Cx Ax xDx xBx DIR Description 3-State Output Enable Input (Active LOW) Register Input Clock Select Input Data Inputs(1) Data Inputs(1) and 3-State Outputs 3-State Outputs Data Inputs(1) and 3-State Outputs Direction Control Input
TVSOP TOP VIEW
NOTE: 1. These pins have "Bus-Hold." All other pins are standard inputs, outputs, or I/Os.
c
1998 Integrated Device Technology, Inc.
3
DSC-123456
IDT74ALVCHG162280 3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLES(1)
A-TO-B STORAGE (OE = L, DIR = H)
Inputs SEL H L L CLK X Ax X L H
1Bx 1B0(2)
C-TO-D STORAGE (OE = L)
Inputs
2Bx 2B0(2)
Outputs SEL H L L
Outputs Cx X L H
1Dx 1D0(2) 2Dx 2D0(2)
CLK X
L(3) H(3)
L H
L(3) H(3)
L H
B-TO-A STORAGE (OE = L, DIR = L)
Inputs SEL H H L L CLK
1Bx 2Bx
OUTPUT ENABLE
Output Inputs CLK X OE H L L L SEL X L L H DIR X H L X Ax Z Z Active A0(2) Outputs
1Bx, 2Bx 1Dx, 2Dx
X X L H
L H X X
Ax L(4) H(4) L H
Z Active Z 1B0, 2B0(2)
Z Active Active Active
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition Z = High-Impedance 2. Output level before indicated steady-state input conditions were established. 3. Two CLK edges are needed to propagate the data. 4. Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is LOW and propagates to the second register when SEL is HIGH.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C Symbol VIH VIL IIH IIL IOZH IOZL VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current(2) Input LOW Current(2) High Impedance Output Current (excludes bus-hold pins) Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 3-3.6V Test Conditions VCC = 3V to 3.6V VCC = 3V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 2 -- -- -- -- -- -- --
(1)
Typ.(1) -- -- -- -- -- -- 100 0.1
Max. -- 0.8 ±5 ±5 ± 10 ± 10 -- 40
Unit V V µA µA µA mV µA
Quiescent Power Supply Current Variation
--
--
750
µA
NOTES: 1. Typical values are at Vcc = 3.3V, +25°C ambient. 2. For control I/P's only excludes bus-hold current.
4
IDT74ALVCHG162280 3.3V CMOS 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
VCC = 3.0V VCC = 3.6V
Test Conditions VI = 2.0V VI = 0.8V VI = 0 to 3.6V
Min. 75 75 --
Typ.(2) -- -- --
Max. -- -- ± 500
Unit µA µA
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage (A port to B port) or (C port to D port) (B port to A port) VOL Output LOW Voltage (A port to B port) or (C port to D port) (B port to A port)
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 0°C to + 70°C.
VCC
Test Conditions(1) = 3V to 3.6V IOH = 0.1mA IOH = 8mA IOH = 6mA IOL = 0.1mA IOL = 8mA IOL = 6mA
Min. VCC 0.2 2 2 -- -- --
Max. -- -- -- 0.2 0.8 0.8
Unit V
VCC = 3.0V VCC = 3.0V to 3.6V VCC = 3.0V
V
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 3.3V ± 0.3V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 80 60 Unit pF pF
5
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