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Details, datasheet, quote on part number:74ALVCHR16260
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Datasheet text preview:
IDT74ALVCHR16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages Extended commercial range of 40°C to + 85°C VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Drive Features for ALVCHR16260: Balanced Output Drivers: ±12mA Low switching noise
IDT74ALVCHR16260
applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the Ato-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latchenable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVCHR16260 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCHR16260 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
· 3.3V High Speed Systems · 3.3V and lower voltage computing systems
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using adv a n c e d dual metal technology. The ALVCHR16260 is used in
Functional Block Diagram
O E1B LEA1B
29 30
A -1 B LATC H
12
1B 1:12
LE1B SEL OEA
2
12
28 1
1 B -A LATC H
12
12
A 1:12
12
M U X
1
0
12 12
LE2B
27
2 B -A LATC H
12
LEA2B O E2B
55
A -2 B LATC H
2B 1:12
12
56
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
JULY 1999
DSC-5167/1
IDT74ALVCHR16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA LE1B
2B 3
ABSOLUTE MAXIMUM RATING
56 55 54 53 52 51 50 49 48 47 46 45 O E 2B LEA2B
2B 4
(1)
Unit V V °C mA mA mA mA
NEW16link
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
2B 2 2B 1
GND
2B 5 2B 6
Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
Max. 0.5 to + 4.6 0.5 to VCC + 0.5 65 to + 150 50 to + 50 ± 50 50 ± 100
V CC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A 10 A11 A12 V CC
1B 1 1B 2
V CC
2B 7 2B 8 2B 9
GND
2B 1 0 2B 1 1 2B 1 2 1B 1 2 1B 1 1 1B 1 0
44 S O 5 6 -1 S O 5 6 -2 4 3 S O 5 6 -3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
GND
1B 9 1B 8 1B 7
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NEW16link
V CC
1B 6 1B 5
NOTE: 1. As applicable to the device type.
GND
1B 3
GND
1B 4
LE2B SEL
LEA1B O E 1B
SSOP/ TSSOP/TVSOP TOP VIEW
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVCHR16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names Ax(1:12)
1Bx(1:12) 2Bx(1:12)
I/O I/O I/O I/O I I I I I I I I
Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus. (1) Bidirectional Data Port 1B. Connected to the even path or even bank of memory. (1) Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory. (1) Latch Enable Input for A-1B latch. The latch is open when LEA1B is HIGH. Data from the A port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B latch. The latch is open when LEA2B is HIGH. Data from the A port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for 1B-A latch. The latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition of LE1B. Latch Enable Input for 2B-A latch. The latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition of LE2B. 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B port to A port. When LOW, SEL enables data transfer from 2B port to A port. Output Enable for A port (Active LOW) Output Enable for 1B port (Active LOW) Output Enable for 2B port (Active LOW)
LEA1B LEA2B LE1B LE2B SEL OEA OE1B OE2B
NOTE: 1. These pins have "Bus-Hold." All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLES (1) B TO A (OEB = H)
Inputs
1Bx 2Bx
A TO B (OEB = H)
Outputs LE2B X X X H H L X OEA L L L L L L H Ax H L A0(2) H L A0(2) Z
Ax H L H L H L X X X X X Inputs L E A1B L E A2B H H H H H L L L X X X X H L L H H L X X X X O E 1B L L L L L L L H L H L O E 2B L L L L L L L H H L L
1B x
Outputs
2B x
H L X X X X X
X X X H L X X
SEL H H H L L L X
LE1B H H L X X X X
H L H L
1B 0 1B 0 ( 2) ( 2)
H L
2B0(2) 2B0(2)
H L
2B0(2)
1B0(2)
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established.
Z A c ti v e Z A c ti v e
Z Z A c ti v e A c ti v e
3
IDT74ALVCHR16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ± 10 ± 10 1.2 -- 40 µA µA V mV µA µA V Unit V
--
--
750
µA
NEW16link
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
VCC = 3.0V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2.0V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ± 500
Unit µA µA µA
NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient.
4
IDT74ALVCHR16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA VCC = 2.7V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8
NEW16link
Unit V
VCC = 2.3V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 2.5V ± 0.2V Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 37 4 VCC = 3.3V ± 0.3V Typical 41 7 Unit
pF pF
5
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