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Details, datasheet, quote on part number:74ALVCHR16270
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Datasheet text preview:
IDT74ALVCHR16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages Extended commercial range of 40°C to + 85°C VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Drive Features for ALVCHR16270: Balanced Output Drivers: ±12mA Low switching noise
IDT74ALVCHR16270
CMOS technology. The ALVCHR16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lowerfrequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. The ALVCHR16270 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCHR16270 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
· 3.3V High Speed Systems · 3.3V and lower voltage computing systems
DESCRIPTION:
This registered bus exchanger is built using advanced dual metal
FUNCTIONAL BLOCK DIAGRAM
CLK
29
2
CLKEN1B
27
CLKEN2B
30
CLKENA1
CLKENA2 OEB
55
C1
56
1D
SEL
28
OEA
1
1D C1
CE C1 1D
23
1B1
A1
8
0 1
CE C1 1D
6
2B 1
CE C1 1D
CE C1 1D
CE C1 1D 1 o f 1 2 C h a n n e ls
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
JUNE 1999
DSC-4578/-
IDT74ALVCHR16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
FUNCTION TABLES
Inputs
(1)
Outputs
OUTPUT ENABLE
O EB H L H L Ax Z Z A c ti v e Active
1Bx, 2Bx
OEA CLKEN1B
2B 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 S O 5 6 -1 S O 5 6 -2 4 3 S O 5 6 -3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 44
OEB CLKENA2
2B 4
CL K
O EA H H L L
Z A c ti v e Z Active
O u tp u ts
GND
2B 2 2B 1
GND
2B 5 2B 6
A-TO-B STORAGE (OEB = L AND OEA = H)
In p u ts CL KENA1 L L L L H H H CL KENA2 H H L L L L H CL K X X X Ax X X L H L H X
1B x 1BO(2) 1BO(2) 2B x 2BO(2) 2BO(2)
V CC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A 10 A 11 A12 V CC
1B 1 1B 2
V CC
2B 7 2B 8 2B 9
L(3) H(3)
1BO(2) 1BO(2) 1BO(2)
L H L H
2BO(2)
GND
2B 1 0 2B 1 1 2B 1 2 1B 1 2 1B 1 1 1B 1 0
B-TO-A STORAGE (OEA = L AND OEB = H)
Inputs CL KEN1B H X L L X X CL KEN2B X H X X L L CL K X X SEL H L H H L L
1Bx 2Bx
Outputs X X L H X X X X X X L H Ax AO(2) AO(2) L H L H
GND
1B 9 1B 8 1B 7
V CC
1B 6 1B 5
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition 2. Output level before the indicated steady-state input conditions were established. 3. Two CLK edges are needed to propagate data.
GND
1B 3
GND
1B 4
CLKEN2B SEL
CLKENA1 CLK
SSOP/ TSSOP/TVSOP TOP VIEW
2
IDT74ALVCHR16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names Ax(1:12)
1Bx(1:12) 2Bx(1:12)
I/O I/O I/O I/O I I I I I I I I
Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) Clock Input Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-2B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the 1B-A Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the 2B-A Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port. Synchronous Output Enable for A Port (Active LOW) Synchronous Output Enable for B Port (Active LOW)
CLK CLKENA1 CLKENA2 CLKEN1B CLKEN2B SEL OEA OEB
NOTE: 1. These pins have "Bus-Hold." All other pins are standard inputs, outputs, or I/Os.
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V °C mA mA mA mA
NEW16link
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NEW16link
Max. 0.5 to + 4.6 0.5 to VCC + 0.5 65 to + 150 50 to + 50 ± 50 50 ± 100
NOTE: 1. As applicable to the device type.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
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IDT74ALVCHR16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. -- -- 0.7 0.8 ±5 ±5 ± 10 ± 10 1.2 -- 40 µA µA V mV µA µA V Unit V
Quiescent Power Supply Current Variation
--
--
750
µA
NEW16link
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
VCC = 3.0V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2.0V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ± 500
Unit µA µA µA
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IDT74ALVCHR16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA VCC = 2.7V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8
NEW16link
Unit V
VCC = 2.3V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical -- -- VCC = 3.3V ± 0.3V Typical -- -- Unit pF pF
5
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