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Details, datasheet, quote on part number:74FCT16823T
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Datasheet text preview:
IDT74FCT16823AT/CT/ET FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT REGISTER
IDT74FCT16823AT/CT/ET
FEATURES:
· · · · · · · ·
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1µA (max.) VCC = 5V ± 10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C · Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT16823T 18-bit bus interface registers are built using advanced, dual metal CMOS technology. These high-speed, low-power registers with clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16823T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
2 1O E 1CLR 1C L K 55 1C L K E N 2C L K E N 1 56 2C L K 2OE 2C L R
27
28
29 30
R C D 54 1D 1 2D 1 3 1Q 1 42
R C D 15 2Q 1
T O EIGHT OTHER CHANNELS
T O EIGHT OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2002 Integrated Device Technology, Inc.
1
JUNE 2002
DSC-5438/2
IDT74FCT16823AT/CT/ET FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1C L R 1O E 1Q 1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max 0.5 to +7 0.5 to VCC+0.5 65 to +150 60 to +120 Unit V V °C mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1C L K 1CLKEN 1 D1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(2) TSTG IOUT
VTERM(3) Terminal Voltage with Respect to GND
GND
1Q 2 1Q 3
GND
1 D2 1 D3
VCC
1Q 4 1Q 5 1Q 6
VCC
1 D4 1 D5 1 D6
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . All device terminals except FCT162XXX Output and I/O terminals. 3 . Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
GND
1Q 7 1Q 8 1Q 9 2Q 1 2Q 2 2Q 3
GND
1 D7 1 D8 1 D9 2 D1 2 D2 2 D3
NOTE: 1 . This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names xDx xCLK xC L K E N xC L R xOE xQx Description Data Inputs Clock Inputs Clock Enable Inputs (Active LOW) Asynchronous Clear Inputs (Active LOW) Output Enable Inputs (Active LOW) 3-State Outputs
GND
2Q 4 2Q 5 2Q 6
GND
2 D4 2 D5 2 D6
VCC
2Q 7 2Q 8
VCC
2 D7 2 D8
GND
2Q 9 2O E 2C L R
GND
2 D9 2CLKEN 2C L K
FUNCTION TABLE(1)
xOE H L L H H L L xCLR X L H H H H H Inputs xCLKEN X X H L L L L xCLK X X X xDx X X X L H L H Outputs xQx Z L Q(2) Z Z L H Function High Z Clear Hold Load
SSOP/ TSSOP TOP VIEW
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2 . Output level before indicated steady-state input conditions were established.
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IDT74FCT16823AT/CT/ET FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40°C to +85°C, VCC = 5.0V ±10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = 18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- 80 -- -- Typ.(2) -- -- -- -- -- -- -- -- 0.7 140 100 5 Max. -- 0.8 ±1 ±1 ±1 ±1 ±1 ±1 1.2 250 -- 500 V mA mV µA µA Unit V V µA
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage VCC = Min. VIN = VIH or VIL VOL IOFF Output LOW Voltage Input/Output Power Off Leakage(5) VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V -- -- ±1 µA
NOTES: 1 . For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2 . Typical values are at VCC = 5.0V, +25°C ambient. 3 . Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4 . Duration of the condition can not exceed one second. 5 . This test limit for this parameter is ±5µA at TA = 55°C.
Test Conditions(1) VCC = Max., VO = 2.5V(3) IOH = 3mA IOH = 15mA IOH = 32mA(4) IOL = 64mA
Min. 50 2.5 2.4 2 --
Typ.(2) -- 3.5 3.5 3 0.2
Max. 180 -- -- -- 0.55
Unit mA V V
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IDT74FCT16823AT/CT/ET FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open xOE = xCLKEN = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz 50% Duty Cycle xOE = xCLKEN = GND fi = 5MHz 50% Duty Cycle One Bit Toggling VCC = Max., Outputs Open fCP = 10MHz 50% Duty Cycle xOE = xCLKEN = GND fi = 2.5MHz 50% Duty Cycle Eighteen Bits Toggling Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA µA/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
4.2
7.1(5)
VIN = 3.4V VIN = GND
--
9.2
22.1(5)
NOTES: 1 . For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2 . Typical values are at VCC = 5.0V, +25°C ambient. 3 . Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4 . This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5 . Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6 . IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT16823AT/CT/ET FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74 FCT16823AT Symbol tPLH tPHL Parameter Propagation Delay CLK to xQx Condition(1) CL = 50pF RL = 500 CL = 300pF(5) RL = 500 tPHL tPHZ tPLZ Propagation Delay xCLR to xQx Output EnableTime xOE to xQx CL = 50pF RL = 500 CL = 50pF RL = 500 CL = 300pF(5) RL = 500 tPHZ Output Disable Time xOE to xQx CL = 5pF(5) RL = 500 CL = 50pF) RL = 500 tSU tH tSU tH tW tW tREM tSK(o) Set-up Time HIGH or LOW, xDx to xCLK Hold Time HIGH or LOW, xDx to xCLK Set-up Time HIGH or LOW, xCLKEN to xCLK Hold Time HIGH or LOW, xCLKEN to xCLK xCLK Pulse Width HIGH or LOW xCLR Pulse Width LOW Recovery Time xCLR to xCLK Output Skew(3) CL = 50pF RL = 500 1.5 1.5 1.5 1.5 1.5 3 1.5 3 0 6 6 6 -- 14 12 23 7 8 -- -- -- -- -- -- -- 0.5 1.5 1.5 1.5 1.5 1.5 2 1.5 3 0 3.3 3.3 6 -- 6.1 5.5 12.5 5.2 6.5 -- -- -- -- -- -- -- 0.5 1.5 1.5 1.5 1.5 1.5 1.5 0 2.5 0 3(4) 3(4) 3 -- 4.4 4.4 9 3.6 3.6 -- -- -- -- -- -- -- 0.5 ns ns ns ns ns ns ns ns ns ns ns Min.(2) 1.5 1.5 Max. 10 20 74FCT16823CT Min . ( 2 ) 1.5 1.5 Max. 6 12.5 74FCT16823ET M i n. ( 2 ) 1.5 1.5 Max. 4.4 8 Unit ns
NOTES: 1 . See test circuit and waveforms. 2 . Minimum limits are guaranteed but not tested on Propagation Delays. 3 . Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 4 . This limit is guaranteed but not tested. 5 . This condition is guaranteed but not tested.
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