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Part: 74FCT16841T
Category:
Logic
Description: 20-Bit Transparent Latch
Company: Integrated Device Technology, Inc.
Datasheet: Download 74FCT16841T datasheet File size : 180 kB
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IDT74FCT16841AT/CT FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 20-BIT TRANSPARENT LATCH
FEATURES: DESCRIPTION:
IDT74FCT16841AT/CT
· · · · · · · ·
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1µA (max.) VCC = 5V ±10% High drive outputs (32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C · Available in SSOP and TSSOP packages
The FCT16841T 20-bit transparent D-type latch is built using advanced dual metal CMOS technology. These high-speed, low-power latches are ideal for temporary data storage. They can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable (OE) and Latch Enable (LE) controls are organized to operate each device as two 10-bit latches or one 20-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16841T is ideally suited for driving high capacitance loads and low impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
1O E
1
2OE
28
1L E
56
2L E
29
1D 1
55
D
2
2D 1
42
D
15
C
1Q 1
C
2Q 1
T O NINE OTHER CHANNELS
T O NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-5466/1
IDT74FCT16841AT/CT FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OE 1Q1 1Q2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max 0.5 to +7 0.5 to VCC+0.5 65 to +150 60 to +120 Unit V V °C mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1LE 1D1 1D2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(2) VTERM(3) TSTG IOUT
GND
1Q3 1Q4
GND
1D3 1D4
VCC
1Q5 1Q6 1Q7
VCC
1D5 1D6 1D7
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . All device terminals except FCT162XXX Output and I/O terminals. 3 . Outputs and I/O terminals for FCT162XXX.
GND
1Q8 1Q9 1Q10 2Q1 2Q2 2Q3
GND
1D8 1D9 1D10 2D1 2D2 2D3
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol CI N CO U T Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1 . This parameter is measured at characterization but not tested.
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
PIN DESCRIPTION
Pin Names xDx xLE xOE xQx Data Inputs Latch Enable Inputs (Active HIGH) Output Enable Inputs (Active LOW) 3-State Outputs Description
VCC
2Q7 2Q8
VCC
2D7 2D8
GND
2Q9 2Q10 2OE
GND
2D9 2D10 2LE
FUNCTION TABLE(1)
xDx H L X X Inputs xLE H H L X xOE L L L H Outputs xQx H L Q(2) Z
SSOP/ TSSOP TOP VIEW
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2 . Output Level before xLE HIGH-to-LOW transition.
2
IDT74FCT16841AT/CT FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40°C to +85°C, VCC = 5.0V ±10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max VIN = GND or VCC VCC = Min., IIN = 18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- 80 -- -- Typ.(2) -- -- -- -- -- -- -- -- 0.7 140 100 5 Max. -- 0.8 ±1 ±1 ±1 ±1 ±1 ±1 1.2 250 -- 500 V mA mV µA µA Unit V V µA
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage VCC = Max., VO = VCC = Min. VIN = VIH or VIL VOL IOFF Output LOW Voltage Input/Output Power Off Leakage(5) VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V -- -- ±1 µA
NOTES: 1 . For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2 . Typical values are at VCC = 5.0V, +25°C ambient. 3 . Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4 . Duration of the condition can not exceed one second. 5 . This test limit for this parameter is ±5µA at TA = 55°C.
Test Conditions(1) 2.5V(3) IOH = 3mA IOH = 15mA IOH = 32mA(4) IOH = 64mA
Min. 50 2.5 2.4 2 --
Typ.(2) -- 3.5 3.5 3 0.2
Max. 180 -- -- -- 0.55
Unit mA V V V V
3
IDT74FCT16841AT/CT FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xOE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle xOE = GND xLE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle xOE = GND xLE = VCC Twenty Bits Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit mA µA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
1.5
mA
--
0.9
2.3
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
3
5.5(5)
--
8
20.5(5)
NOTES: 1 . For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2 . Typical values are at VCC = 5.0V, +25°C ambient. 3 . Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4 . This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5 . Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6 . IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
4
IDT74FCT16841AT/CT FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74FCT16841AT Symbol tPLH tPHL Parameter Propagation Delay xDx to xQx (LE = HIGH) Propagation Delay xLE to xQx Condition(1) CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 5pF(3) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500 Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4(5) -- Max. 9 13 12 16 11.5 23 7 8 -- -- -- 0.5 74FCT16841CT Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1 1 3(5) -- Max. 3.8 7.5 3.8 7.5 4.6 9 3.6 3.6 -- -- -- 0.5 ns ns ns ns ns ns ns Unit ns
tPLH tPHL
tPZH tPZL
Output Enable Time xOE to xQx
tPHZ tPLZ
Output Disable Time xOE to xQx
tSU tH tW tSK(o)
Set-Up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(4)
NOTES: 1 . See test circuit and waveforms. 2 . Minimum limits are guaranteed but not tested on Propagation Delays. 3 . This condition is guaranteed but not tested. 4 . Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 5 . This limit is guaranteed but not tested.
5
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