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Details, datasheet, quote on part number:74FCT16V345
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Datasheet text preview:
IDT74FCT16V345 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
FEATURES:
- - - - - - - 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range VCC = 2.5V ±0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SSOP, TSSOP, and TVSOP Packages
IDT74FCT16V345
DESCRIPTION:
The FCT16V345 is a registered address driver built using advanced dual metal CMOS technology. The device is configured with fan out of four for use in high speed synchronous memory applications. The FCT16V345 is ideal for driving memory modules in systems where multiple memory modules are used. If each of the four output banks drives a different module, modules can be added or removed without affecting the signal integrity of the other modules in the system. Dual Clock Enables (CEx) allow use of the FCT16V345 in high speed memory interleaving applications where the clock can be alternately enabled and disabled, allowing the address to be held for additional clock cycles during memory access.
FUNCTIONAL BLOCK DIAGRAM
CE1 OE
1
CE2
56
29 2 8 34
1Q 1
1Q 5
CE D
6 4Q 1
D1
D5
36
CE D
30 4Q 5 41
9
1Q 2
1Q 6
D2
14
CE D
13 4Q 2
D6
42
CE D
37 4Q 6
16
1Q 3
48 43
1Q 7
D3
15
CE D
20 4Q 3 1Q 4
CE D
44 4Q 7 1Q 8
D7
23
55
D4
21
CE D
27 4Q 4
D8
49
CE D
51 4Q 8
CLK
28
INDUSTRIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-3786/-
IDT74FCT16V345 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
CE1
1Q1 2Q1
ABSOLUTE MAXIMUM RATINGS(1)
56 55 54 53 52 51 50 49 48 47 46 45 44 CE2
1Q 8 2Q 8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SO 56-1 SO 56-2 SO 56-3
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current
Max 0.5 to +4.6 0.5 to VCC+0.5 65 to +150 60 to +60
Unit V V °C mA
GND
3Q1 4Q1
GND
3Q 8 4Q 8
V CC D1
1Q2 2Q2
VCC D8
1Q 7 2Q 7
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Non bus-hold input terminals and Vcc terminals. 3. Output, I/O terminals, and bus-hold input terminals.
GND
3Q2 4Q2
GND
3Q 7 4Q 7
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
3v16-link
D2 D3
1Q3 2Q3
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
D7 D6
1Q 6 2Q 6
NOTE: 1. This parameter is measured at characterization but not tested.
GND
3Q3 4Q3
GND
3Q 6 4Q 6
PIN DESCRIPTION
Pin Names OE Dx xQx CLK CEx Description 3-State Output Enable Input (Active LOW) Inputs 3-State Outputs Clock Input Clock Enable (Active LOW)
D4 V CC
1Q4 2Q4
D5 VCC
1Q 5 2Q 5
GND
3Q4 4Q4
GND
3Q 5 4Q 5
CLK
OE
FUNCTION TABLE(1)
Inputs Outputs OE L L L L H Dx X X L H X xQx B(2) B(2) L H Z CEx H X L L X CLK X L X
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition Z = High-Impedance 2. Output level before indicated steady-state input conditions were established.
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IDT74FCT16V345 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC VCC = 2.3V, IIN = 18mA -- Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 0.5 0.5 -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- 0.7 100 0.1 Max. 3.6 3.6 0.7 0.8 ±1 ±1 ±1 ±1 1.2 -- 10 V mV µA µA µA V Unit V
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA VCC = 2.7V VCC = 3V IOL = 12mA IOL = 24mA Test Conditions(1) IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
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IDT74FCT16V345 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD1 Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = VCC 0.6V(3) VCC = Max. Outputs Open OE = GND One Clock Input Bit Toggling No Output Bits Toggling 50% Duty Cycle VCC = Max. Outputs Open OE = GND One Input Bit Toggling Four Output Bits Toggling One Clock Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fcp= 10MHz 50% Duty Cycle OE = CEx = GND At fi= 5MHz 50% Duty Cycle One Input Bit Toggling Four Output Bits Toggling One Clock Input Toggling VCC = Max. Outputs Open fcp = 10MHz 50% Duty Cycle OE = CEx = GND At fi= 2.5MHz 50% Duty Cycle Eight Input Bits Toggling Thirty Two Output Bits Toggling One Clock Input Toggling
NOTES: 1. VCC (max.) = 3.6V 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
Test Conditions(1)
Min. --
Typ.(2) 2 37
Max. 3 50
Unit µA µ A/ MHz
VIN = VCC VIN = GND
--
ICCD2
Dynamic Power Supply Current(4)
VIN = VCC VIN = GND
--
252
300
µ A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
1.63
2.01
mA
VIN = VCC 0.6V VIN = GND
--
1.63
2.04
VIN = VCC VIN = GND
--
5.41
6.51
VIN = VCC 0.6V VIN = GND
--
5.42
6.65
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IDT74FCT16V345 3.3V FAST CMOS REGISTERED ADDRESS LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
VCC = 2.5V±0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tSK(o) tSK(b) Parameter Propagation Delay CLK to xQx Output Enable Time OE to xQx Output Disable Time OE to xQx Set-Up Time HIGH or LOW CEx to CLK Hold Time HIGH or LOW CEx to CLK Set-Up Time HIGH or LOW Dx to CLK Hold Time HIGH or LOW CLK to Dx CLK Pulse Width HIGH or LOW(5) Output Skew(3) Bank Skew(4) Condition(1) CL = 50pF RL = 500 Min. 1.5
(2)
VCC = 2.7V Min. 1.5
(2)
VCC = 3.3V±0.3V Min.(2) 1.5 1.5 1.5 1.2 0 0.8 0 3 -- -- Max. 5.5 6 4.9 -- -- -- -- -- 500 350 Unit ns ns ns ns ns ns ns ns ps ps
Max. 7 7.7 6.2 -- -- -- -- -- 500 350
Max. 6 6.9 5.2 -- -- -- -- -- 500 350
1.5 1.5 2 0 2 0 3 -- --
1.5 1.5 2 0 2 0 3 -- --
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on propagation delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. Skew between any two outputs with a common input signal. This parameter is guaranteed by design. 5. This parameter is guaranteed but not tested.
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