|IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
· 0.5 MICRON CMOS Technology· ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0)· VCC ± 0.3V, Normal Range· VCC to 3.6V, Extended Range· CMOS power levels (0.4µ W typ. static)· Rail-to-Rail output swing for increased noise margin· All inputs, outputs, and I/Os are 5V tolerant· Supports hot insertion· Available in SOIC, SSOP, and TSSOP packages
The LVC125A quadruple bus buffer gate is built using advanced dual metal CMOS technology. The LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated outputenable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. The LVC125A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
· High Output Drivers: ±24mA· Reduced system switching noise
· 5V and 3.3V mixed voltage systems· Data communication and telecommunication systems
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Symbol VTERM Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, < 0 Continuous Current through each VCC or GND Max 50 ±100 Unit °C mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5.5 6.5 Max. 6 8 Unit pF
Pin Names xA xY Data Inputs 3-State Outputs Description Output-Enable Inputs (Active LOW)
NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
Following Conditions Apply Unless Otherwise Specified: Operating Condition: to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN VO 5.5V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC mV µA VCC ±10 µA Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC to 2.7V VCC to 3.6V VCC to 2.7V VCC to 3.6V VCC to 5.5V Test Conditions Min. 2 Typ.(1) Max. µA V Unit V
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC to 3.6V IOH 0.1mA IOH 6mA IOH 12mA Min. VCC Max. V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. + 85°C.