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Details, datasheet, quote on part number:74LVC137A
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Datasheet text preview:
IDT74LVC137A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER, WITH ADDRESS LATCHES
FEATURES:
0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1.27mm pitch SOIC, 0.635mm pitch QSOP, 0.65mm pitch SSOP, 0.65mm pitch TSSOP packages Extended commercial range of 40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 2.3V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion
IDT74LVC137A
DESCRIPTION:
The LVC137A 3-line to 8-line decoder/demultiplexer is built using advanced dual metal CMOS technology. The LVC137A is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. When the latch enable (G2A) input is low, the LVC137A acts as a decoder/demultiplexer. When G2A transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the outputs independently of the select or latchenable inputs. All of the outputs are forced high if G1 is low or G2B is high. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC137A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
Drive Features for LVC137A: High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
Functional Block Diagram
A
1 15
Y0
14
Y1
13
S e le c t I n p u ts
B
2
Y2
12
Y3 D a ta O u tp u ts Y4
3
11
C
10
Y5
9
Y6 L a tc h E n a b le G 2A
4 8
Y7 G 2B G1
5 6
O u tp u t E n a b le s
EXTENDED COMMERCIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
MAY 1999
DSC-4753/1
IDT74LVC137A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A B C G 2A G 2B G1 Y7 GND 1 2 3 4 5 6 7 8 16 15 14 13 S O 1 6 -7 S O 1 6 -8 12 S O 1 6 -9 S O 1 6 -1 0 1 1 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
LVC QUAD Link
Max. 0.5 to +6.5 0.5 to +6.5 65 to +150 50 to +50 50 ± 100
Unit V V °C mA mA mA
SOIC/ SSOP/ TSSOP/ QSOP TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
PIN DESCRIPTION
Pin Names G1 G2A G2B Yx A, B, C Description Output Enable Latch Enable (Active LOW) Output Enable (Active LOW) Data Outputs Select Data Inputs
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance
LVC QUAD Link
Conditions VIN = 0V VOUT = 0V VIN = 0V
Typ. 4.5 5.5 6.5
Max. 6 8 8
Unit pF pF pF
NOTE: 1. As applicable to the device type.
FUNCTION TABLE(1)
Latch Enable G2A X X L L L L L L L L H Inputs Output Enable G1 G2B X H L X H L H L H L H L H L H L H L H L H L Select Inputs Outputs
C X X L L L L H H H H X
B X X L L H H L L H H X
A X X L H L H L H L H X
Y0 H H L H H H H H H H
Y1 Y2 Y3 Y4 Y5 Y6 H H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H Outputs corresponding to stored address = L; all other outputs = H
Y7 H H H H H H H H H L
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
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IDT74LVC137A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°c to +85°c
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- 0.7 100 -- ± 50 1.2 -- 10 µA V mV µA Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VI = 0 to 5.5V VO = 0 to 5.5V Min. 1.7 2 -- -- -- -- Typ.(1) -- -- -- -- -- -- Max. -- -- 0.7 0.8 ±5 ± 10 µA µA V Unit V
Quiescent Power Supply Current Variation
One input at VCC 0.6V other inputs at VCC or GND
--
--
500
µA
LVC QUAD Link
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA VCC = 2.7V VCC = 3.0V IOL = 12mA IOL = 24mA 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
LVC QUAD Link
Unit V
VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to +85°C.
c
1998 Integrated Device Technology, Inc.
3
DSC-123456
IDT74LVC137A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V±0.2V Symbol Parameter CPD Power Dissipation Capacitance Test Conditions CL = 0pF, f = 10Mhz Typical -- VCC = 3.3V±0.3V Typical 25 Unit pF
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tW tSU tH tSK(0) Parameter Propagation Delay A to B, C to Yx Propagation Delay G2A to Yx Propagation Delay G1 or G2B to Yx Pulse Duration, G2A Setup Time, at A, B, and C before G2A Hold Time, at A, B, and C after G2A Output Skew(2) Min. -- -- -- 3 2 1.2 --
(1)
VCC = 2.7V Min. -- -- -- 3 2.1 1.1 -- Max. 6.9 8.5 8.2 -- -- -- -- VCC = 3.3V±0.3V Min. 1 1 1 3 1.9 1.1 -- Max. 6.2 7.8 7.5 -- -- -- 1 Unit ns ns ns ns ns ns ns
VCC = 2.5V±0.2V Max. -- -- -- -- -- -- --
NOTES: 1. See test circuits and waveforms. TA = 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC137A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 2.5V ±0.2V 2 x Vcc Vcc VCC / 2 150 150 30
TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY
VCC(2)= 3.3V ±0.3V & 2.7V 6 2.7 1.5 300 300 50 Unit V V V mV mV pF
LVC QUAD Link
S A M E PH A S E IN P U T TR A N S IT I O N tP L H O U TPU T tP L H O P P O S IT E P H A S E IN P U T TR A N S IT I O N tP H L tP H L
V IH VT 0V VOH VT VOL V IH VT 0V
L V C Q U A D L in k
TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 P u ls e G e n e ra to r
( 1 , 2)
V LOAD O pen GND
ENABLE AND DISABLE TIMES
ENABLE CO NTRO L IN P U T tP Z L tP L Z V L O A D /2 VT tP H Z VT 0V D IS A B L E V IH VT 0V V L O A D /2 V LZ VOL V OH V HZ 0V
L V C Q U A D L in k
V IN D . U .T .
V OUT
RT
500 CL
L V C Q U A D L in k
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
O U TPU T S W IT C H N O R M ALLY CLO SED LO W tP Z H O UTPUT S W IT C H N O R M ALLY OP EN H IG H
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA IN P U T T IM IN G IN P U T SYNCH RONOUS C O N TR O L
LVC QUAD Link
tS U
tH
GND Open
tR E M
V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
L V C Q U A D L in k
OUTPUT SKEW - tsk (x)
IN P U T tP L H 1 tP H L 1
V IH VT 0V VOH
ASYNC HRONOUS C O N TR O L
tS U
tH
PULSE WIDTH
L O W -H IG H -L O W PU LSE tW H I G H - L O W - H IG H PU LSE VT
L V C Q U A D L in k
O UTPUT 1
tS K (x)
tS K (x)
VT V OL V OH
VT
O UTPUT 2 tP L H 2 tP H L2
VT VOL
tS K (x ) = tPLH2 - tPLH1 or tPHL2 - tPHL1
L V C Q U A D L in k NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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