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Details, datasheet, quote on part number:74LVC1G79A
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Datasheet text preview:
IDT74LVC1G79A 3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP, 5 VOLT TOLERANT I/O
FEATURES:
0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.65mm pitch PSOP package Extended commercial range of 40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 1.65V to 3.6V, Extended Range VCC = 2.5V ±0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion
IDT74LVC1G79A
DESCRIPTION
This single positive-edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The LVC1G79A is designed for 2.3V to 3.6V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The LVC1G79A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
Drive Features for LVC1G79A: High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
C LK
2
C C C TG
4
Q
C
C
C
C
D
1
TG
TG
TG
C
C
C
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4912/-
IDT74LVC1G79A 3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND Max. 0.5 to +6.5
(1) Unit V °C mA mA mA
LVC 1G Link
D C LK GND
1 2 S O 5 -1 3
PSOP TOP VIEW
5
VCC
65 to +150 50 to +50 50 ± 100
4
Q
PIN DESCRIPTION
Pin Names CLK D Q Description Data Inputs Data Inputs Data Output (1) Output Q H L Q0
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC 1G Link
FUNCTION TABLE
Inputs CLK L
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH transition
D H L X
NOTE: 1. As applicable to the device type.
Q0 = Level of Q before the indicated steady-state input conditions were established.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC1G79A 3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C To +85°C
Symbol VIH Parameter Input HIGH Voltage Level VCC VCC VCC VCC VCC VCC VCC Test Conditions = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 3.6V VI = 0 to 5.5V VI = 0 to 5.5V Min. Typ.(1) Max. 0.65 x VCC -- -- 1.7 -- -- 2 -- -- -- -- 0.35 x VCC -- -- 0.7 -- -- 0.8 -- -- ±5 -- -- -- -- -- -- -- 0.7 100 -- -- -- ± 10 1.2 -- 10 10 500 µA
LVC 1G Link
Unit V V
VIL
Input LOW Voltage Level
V µA µA V mV µA
IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC
Input Leakage Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current
VCC = 3.6V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V
VIN = GND or VCC 3.6 < Vin < 5.5V (2)
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies to 3-state outputs in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 1.65V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 8mA IOH = 12mA IOH = 24mA IOL = 0.1mA IOL = 4mA IOL = 8mA IOL = 12mA IOL = 24mA Min. VCC 0.2 1.2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.45 0.7 0.4 0.55
LVC 1G Link
Unit V
VCC = 1.65V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 1.65V to 3.6V VCC = 1.65V VCC = 2.3V VCC = 2.7V VCC = 3.0V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to +85°C.
3
IDT74LVC1G79A 3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 1.8V±0.15V Symbol CPD Parameter Power Dissipation Capacitance Test Conditions CL = 0pF, f = 10Mhz Typical -- VCC = 2.5V±0.2V Typical -- VCC = 3.3V±0.3V Typical -- Unit pF
SWITCHING CHARACTERISTICS
Symbol fMAX tPLH tPHL tW tSU tSU tH Parameter Propagation Delay CLK to Q Pulse Width, CLK HIGH or LOW Setup Time, data before CLK, HIGH Setup Time, data before CLK, LOW Hold Time, data after CLK Min. 1 5 5 5 2
(1) VCC = 2.5V ± 0.2V Min. 1 3.3 3 3 1 Max. 7 -- -- -- -- VCC = 2.7V Min. -- 3.3 3 3 1 Max. 6 -- -- -- -- VCC = 3.3V ± 0.3V Min. 1 3.3 3 3 0 Max. 5.2 -- -- -- -- Unit MHz ns ns ns ns ns
VCC = 1.8V ± 0.15V Max. 14 -- -- -- --
NOTE: 1. See test circuits and waveforms. TA = 40°C to + 85°C.
4
IDT74LVC1G79A 3.3V CMOS SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50
TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
LVC 1G Link
VCC(1)= 2.7V
S A M E PHASE IN P U T TRANSITION tP L H OUTPUT tP L H O P P O S IT E PHASE IN P U T TRANSITION tP H L tP H L
V IH VT 0V VOH VT VOL V IH VT 0V
L V C 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 P u ls e G e n e r a to r
( 1 , 2)
ENABLE AND DISABLE TIMES
EN ABLE C O N TR O L IN P U T tP Z L OU TPU T S W IT C H N OR M ALLY CLO SED LOW tP Z H OU TPU T S W IT C H N OR M ALLY OPEN H IG H V L O A D /2 VT tP H Z VT 0V tP L Z D IS A B L E V IH VT 0V V L O A D /2 V O L +VLZ VOL VOH V O H -VLZ 0V
L V C 1G Link
V LO AD Open GND
V IN D . U .T .
V O UT
RT
500 CL
L V C 1G Link
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA IN P U T T IM IN G IN P U T V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
L V C 1G Link
tS U
tH
GND Open
LVC 1G Link
tR E M A S Y N C H RO N O U S C O N TR O L S Y N C H RO N O U S C O N TR O L
tS U
PULSE WIDTH
L O W - H IG H - L O W PU LSE tW H I G H - L O W -H I G H PU LSE VT
L V C 1G Link
tH
VT
5
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