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Part: 74LVC1G86A
Category:
Description:
Company: Integrated Device Technology, Inc.
Datasheet: Download 74LVC1G86A datasheet File size : 132 kB
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Datasheet text preview:
IDT74LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O
FEATURES:
0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.65mm pitch PSOP package Extended commercial range of 40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 1.65V to 3.6V, Extended Range VCC = 2.5V ±0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion Drive Features for LVC1G86A: High Output Drivers: ±24mA Suitable for heavy loads
IDT74LVC1G86A
DESCRIPTION:
This single 2-input exclusive-OR gate is built using advanced dual metal CMOS technology. The LVC1G86A is designed for 1.65V to 3.6V VCC operation and performs the Boolean function Y = A B or Y = AB + AB in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. The LVC1G86A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
APPLICATIONS:
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
Functional Block Diagram
A
1 4 2
PIN CONFIGURATION
A
Y
1 2 S O 5 -1 3
5
VCC
B GND
B
4
Y
PSOP TOP VIEW
PIN DESCRIPTION
Pin Names A, B Y Description Data Inputs Data Output
FUNCTION TABLE (1)
Inputs A L L H H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level
B L H L H
Output Y L H H L
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
MAY 1999
DSC-4762/1
IDT74LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE (1) Unit V V °C mA mA mA
LVC 1G Link
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC 1G Link
Max. 0.5 to + 6.5 0.5 to +6.5 65 to + 150 50 to + 50 50 ± 100
NOTE: 1. As applicable to the device type.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C To +85°C
Symbol VIH Parameter Input HIGH Voltage Level VCC VCC VCC VCC VCC VCC VCC Test Conditions = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 3.6V VI = 0 to 5.5V VI = 0 to 5.5V Min. Typ.(1) Max. 0.65 x VCC -- -- 1.7 -- -- 2 -- -- -- -- 0.35 x VCC -- -- 0.7 -- -- 0.8 -- -- ±5 -- -- -- -- -- -- -- 0.7 100 -- -- -- ± 10 1.2 -- 10 10 500 µA
LVC 1G Link
Unit V V
VIL
Input LOW Voltage Level
V µA µA V mV µA
IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC
Input Leakage Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current
VCC = 3.6V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V
VIN = GND or VCC 3.6 < Vin < 5.5V (2)
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies to 3-state outputs in the disabled state only.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 1.65V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 8mA IOH = 12mA IOH = 24mA IOL = 0.1mA IOL = 4mA IOL = 8mA IOL = 12mA IOL = 24mA Min. VCC 0.2 1.2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.45 0.7 0.4 0.55
LVC 1G Link
Unit V
VCC = 1.65V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 1.65V to 3.6V VCC = 1.65V VCC = 2.3V VCC = 2.7V VCC = 3.0V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to +85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 1.8V±0.15V Symbol CPD Parameter Power Dissipation Capacitance Test Conditions CL = 0pF, f = 10Mhz Typical -- VCC = 2.5V±0.2V Typical -- VCC = 3.3V±0.3V Typical -- Unit pF
SWITCHING CHARACTERISTICS
Symbol Parameter tPLH Propagation Delay A or B to Y tPHL Min. 1
(1) VCC = 2.5V±0.2V Min. 1 Max. 7.6 VCC = 2.7V Min. -- Max. 5.6 VCC = 3.3V±0.3V Min. 1 Max. 4.6 Unit ns
VCC = 1.8V±0.15V Max. 13.6
NOTE: 1. See test circuits and waveforms. TA = 40°C to + 85°C.
3
IDT74LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50
TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
LVC 1G Link
VCC(1)= 2.7V
S A M E PHASE IN P U T TRANSITION tP L H OU TPU T tP L H O P P O S IT E PHASE IN P U T TRANSITION tP H L tP H L
V IH VT 0V VOH VT VOL V IH VT 0V
L V C 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 P u ls e G e n e r a to r
( 1 , 2)
ENABLE AND DISABLE TIMES
EN ABLE CONTROL IN P U T tP Z L OU TPU T S W IT C H N OR M ALLY CLO S E D LOW tP Z H OUTPUT S W IT C H N OR M ALLY OPEN H IG H V L O A D /2 VT tP H Z VT 0V tP L Z D IS A B L E V IH VT 0V V L O A D /2 V O L +VLZ VOL VOH V O H -VLZ 0V
L V C 1G Link
V LO AD Open GND
V IN D . U .T .
V O UT
RT
500 CL
L V C 1G Link
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA IN P U T T IM IN G IN P U T V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
L V C 1G Link
tS U
tH
GND Open
LVC 1G Link
tR E M ASYN C H RONO U S C O N TR O L SYN C H RONO U S C O N TR O L
tS U
PULSE WIDTH
L O W - H IG H - L O W PU LSE tW H I G H - L O W -H I G H PU LSE VT
L V C 1G Link
tH
VT
4
IDT74LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC (1) = 1.8V ± 0.15V 2 x Vcc Vcc VCC / 2 150 150 30 Unit V V V mV mV pF
LVC 1G Link
PROPAGATION DELAY
S A M E PHASE I N P U T TRANSITIO N tP L H O U TPU T tP L H O P P O S IT E PHASE I N P U T TRANSITIO N tP H L V IH VT 0V
L V C 1G Link
tP H L
V IH VT 0V VOH VT VOL
TEST CIRCUITS FOR ALL OUTPUTS
V CC V LOAD O pen 1000 P u ls e G e n e r a to r RT
(1)
ENABLE AND DISABLE TIMES
E N A BLE C O N TR O L IN P U T tP Z L O U TPU T S W IT C H N O R M ALLY CLOSE D LO W tP Z H O U TPU T S W IT C H N O R M ALLY OPEN H IG H V L O A D /2 VT tP H Z VT tP L Z D IS A B L E V IH VT 0V V L O A D /2 V O L + VLZ V OL V OH V O H VHZ
GND
V IN D .U .T .
V OUT
CL
1000
L V C 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
0V 0V NOTE: L V C 1G Link 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V
L V C 1G Link
DATA IN P U T T IM IN G IN P U T
tS U
tH
GND Open
LVC 1G Link
tR E M ASYNCHRONOUS C O N TR O L SYN CHRONOUS C O N TR O L
PULSE WIDTH
tS U
tH
L O W - H IG H - L O W P U LS E tW H IG H -L O W -H IG H P U LS E
VT
VT
L V C 1G Link
5
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