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Details, datasheet, quote on part number:74LVCH16827A
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Datasheet text preview:
IDT74LVCH16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES: DESCRIPTION:
IDT74LVCH16827A
· Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · CMOS power levels (0.4µ W typ. static) µ · All inputs, outputs, and I/O are 5V tolerant · Supports hot insertion · Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES: APPLICATIONS:
· High Output Drivers: ±24mA · Reduced system switching noise
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
This 20-bit buffer is built using advanced dual metal CMOS technology. The 20-bit bus driver provides high-performance bus interface buffering for wide data/address paths or busses carrying parity. Two pair of NANDed output enable controls offer maximum control flexibility and are organized to operate the device as two 10-bit buffers or one 20-bit buffer. Flowthrough organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVCH16827A buffer is ideally suited for driving high capacitance loads and low impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16827A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16827A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OE1 1OE2
1 56
2OE1 2OE2
28 29
1A1
55
2
1Y1
2A1
42
15
2Y1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4072/2
IDT74LVCH16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OE1 1Y1 1Y2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND 0.5 to +6.5 65 to +150 50 to +50 50 ±100
Unit V °C mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE2 1A1 1A2
TSTG IOUT IIK IOK ICC ISS
GND
1Y3 1Y4
GND
1A3 1A4
VCC
1Y5 1Y6 1Y7
VCC
1A5 1A6 1A7
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N COUT CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
GND
1Y8 1Y9 1Y10 2Y1 2Y2 2Y3
GND
1A8 1A9 1A10 2A1 2A2 2A3
NOTE: 1 . As applicable to the device type.
GND
2Y4 2Y5 2Y6
GND
2A4 2A5 2A6
PIN DESCRIPTION
Pin Names xOEx xAx xYx Data Inputs(1) 3-State Outputs Description Output Enable Inputs (Active LOW)
VCC
2Y7 2Y8
VCC
2A7 2A8
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
2Y9 2Y10 2OE1
GND
2A9 2A10 2OE2
FUNCTION TABLE(1)
Inputs xOE1 L L H X xOE2 L L X H xAx L H X X Outputs xYx L H Z Z
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTE: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
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IDT74LVCH16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- 0.7 100 -- -- -- ±50 1.2 -- 10 10 500 µA V mV µA VCC = 3.6V VO = 0 to 5.5V -- -- ±10 µA Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 ±5 µA V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES: 1 . Typical values are at VCC = 3.3V, +25°C ambient. 2 . This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
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IDT74LVCH16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Buffer/Driver Outputs enabled Power Dissipation Capacitance per Buffer/Driver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xYx Output Enable Time xOEx to xYx Output Disable Time xOEx to xYx Output Skew(2) -- -- -- 500 ps 1.5 6 1.5 5.7 ns 1.5 8 1.5 7 ns Min. 1.5 Max. 5 VCC = 3.3V ± 0.3V Min. 1.5 Max. 4.4 Unit ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 . Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVCH16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
OUTPUT 1
tSK (x)
tSK (x)
VT
LVC Link
OUTPUT 2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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