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Part: 74LVCH2573A
Category:
Logic
Description: 3.3V CMOS Octal Transparent D-type Latch With 3-STATE Outputs, 5V Tolerant I/O, And Bus-hold
Company: Integrated Device Technology, Inc.
Datasheet: Download 74LVCH2573A datasheet File size : 143 kB
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Datasheet text preview:
IDT74LVCH2573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD
· 0.5 MICRON CMOS Technology · ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · CMOS power levels (0.4µ W typ. static) µ · Rail-to-rail output swing for increased noise margin · All inputs, outputs, and I/O are 5V tolerant · Supports hot insertion · Available in SOIC, SSOP, QSOP, and TSSOP packages
IDT74LVCH2573A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
· Balanced Output Drivers: ±12mA · Low switching noise
APPLICATIONS:
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
The LVCH2573A octal transparent D-type latch is built using advanced dual metal CMOS technology. The device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads, and is particularly suitable for implementing buffer registers, input-output (I/ O) ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The LVCH2573A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been developed to drive ±12mA at the designated thresholds. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. The LVCH2573A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OE
1
LE
11
C1
1D 2 1D
19
1Q
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4942/1
IDT74LVCH2573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
1D 2D 3D 4D 5D 6D 7D 8D
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max
Unit V °C mA mA mA
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
VTERM TSTG IOUT IIK IOK ICC ISS
Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
0.5 to +6.5 65 to +150 50 to +50 50 ±100
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
GND
LE
SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW
NOTE: 1 . As applicable to the device type.
PIN DESCRIPTION
Pin Names OE LE xD xQ Description Output Enable Inputs (Active LOW) Latch Enable Input Data Inputs(1) 3-State Data Outputs
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH LATCH)(1)
Inputs xD H L X X LE H H L X OE L L L H Outputs xQ H L Q( 2 ) Z
NOTES: 1 . H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High-Impedance 2 . Output level before the indicated steady-state input conditions were established.
2
IDT74LVCH2573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- 0.7 100 -- -- -- ±50 1.2 -- 10 10 500 µA V mV µA VCC = 3.6V VO = 0 to 5.5V -- -- ±10 µA Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 ±5 µA V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES: 1 . Typical values are at VCC = 3.3V, +25°C ambient. 2 . This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1 . Pins with Bus-Hold are identified in the pin description. 2 . Typical values are at VCC = 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- ±500
Unit µA µA µA
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IDT74LVCH2573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 4mA IOH = 6mA IOH = 4mA IOH = 8mA IOH = 6mA IOH = 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW tSU tH tSK(o) Parameter Propagation Delay xD to xQ Propagation Delay LE to xQ Output Enable Time OEx to xQ Output Disable Time OEx to xQ Pulse Duration, LE HIGH Setup Time, data before LE Hold Time, data after LE Output Skew(2) 3.3 2.5 1.5 -- -- -- 3.3 2.5 1.5 -- -- -- 500 ns ns ns ps 1.5 7 1.5 6.5 ns 1.5 9.5 1.5 8.5 ns 1.5 9.5 1.5 8.5 ns Min. 1.5 Max. 9 VCC = 3.3V ± 0.3V Min. 1.5 Max. 8 Unit ns
--
--
--
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 . Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH2573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL VOUT
VLOAD Open GND CONTROL INPUT
Propagation Delay
ENABLE DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
tPZL OUTPUT SWITCH NORMALLY VLOAD LOW tPZH OUTPUT SWITCH NORMALLY GND HIGH VLOAD/2 VT tPHZ VT 0V
tPLZ
LVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2 . Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
OUTPUT 2 tPLH2 tPHL2
VT
Pulse Width
LVC Link
LVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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