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Part: 821034
Category:
Description: Quad PCM Codec With Programmable Gain Control
Company: Integrated Device Technology, Inc.
Datasheet: Download 821034 datasheet File size : 78 kB
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QUAD PCM CODEC WITH PROGRAMMABLE GAIN
FEATURES:
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IDT821034
DESCRIPTION:
The IDT821034 is a single-chip, four channel PCM CODEC with onchip filters and programmable gain setting. This device provides both µ-Law and A-Law companding digital-to-analog and analog-to-digital conversions based on ITU-T G.711 - G.714 specifications. The digital filters in IDT821034 provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. The IDT821034 has a flexible PCM interface with software selectable timing modes and independently programmable time slot for each transmit and receive channel. It also integrates the SLIC signaling functions through internal registers. The CODEC and SLIC control/status registers are accessed via the Serial Control Interface. The IDT821034 can be used in digital telecommunication applications such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Data Access Unit.
4 channel CODEC with on-chip digital filters Software Selectable A-law/µ-law companding Programmable gain setting Automatic master clock frequency selection: 2.048MHz, 4.096 MHz or 8.192MHz Flexible PCM interface with up to 128 programmable time slots, data rate from 512 kbits/s to 8.192 Mbits/s 5 SLIC signaling pins per channel Flexible Serial Control Interface to microcontroller Software programmable timing modes TTL and CMOS compatible digital I/O Meets or exceeds ITU-T G.711 - G.714 requirements +5 V single power supply Low power consumption: 100mW Typ. Operating temperature range: -40 °C to +85 °C Packages available: 52 pin PQFP
FUNCTIONAL BLOCK DIAGRAM
GSX0 VFXI0
+
+2.5V
A/D Channel 0 D/A SLIC Interface I/O Channel 1 Channel 2 Channel 3 DSP
PCM Interface
DX DR FS BCLK TSX
VFRO0 O_0(4 - 2) I/O_0(1 - 0)
Serial Control Interface
CO CI CS CCLK
Timing
MCLK
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
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© 2003 Integrated Device Technology, Inc.
MAY 13, 2003
DSC-6032/3
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
VFRO0 I/O1_1 I/O1_0 I/O0_1 27 26 25 24 23 22 21 VFXI0 GSX0 O1_4 O1_3 O1_2 O0_4 30 O0_3 29 O0_2 28 CNF 36
39
38
37
35
34
33
32
GNDA GNDA VFXI1 GSX1 VFRO1 VDDA GNDA VDDA VFRO2 GSX2 VFXI2 GNDA GNDA
40 41 42 43 44 45 46 47 48 49 50 51 52 10 11 12 13 1 2 3 4 5 6 7 8 9
31
I/O0_0 GND CS CI CO CCLK BCLK MCLK FS TSX DR VDD DX
52-Pin PQFP
20 19 18 17 16 15 14
GSX3
VFRO3
VFXI3
I/O2_1
I/O2_0
I/O3_1
PIN DESCRIPTION
Name GNDA Type -Pin Number 46 51 52 40 41 47 45 3 48 44 37 2 49 43 38 1 50 42 39 9 10 11 4 5 6 Description Analog Ground. All ground pins should be connected to the ground plane of the circuit board.
VDDA VFRO3 VFRO2 VFRO1 VFRO0 GSX3 GSX2 GSX1 GSX0 VFXI3 VFXI2 VFXI1 VFXI0 O3_4 O3_3 O3_2 O2_4 O2_3 O2_2
-O
+5 V Analog Power Supply. This pin should be bypassed to ground using 0.1µF capacitor. All power supply pins should be connected to the power plane of the circuit board. Voice Frequency Receiver Output. This is the output of receive power amplifier. It can drive 2000 (or greater) load. Gain Setting Transmit Amplifier Output. This pin is the output of the gain setting amplifier, and the input to the differential transmit filter. It should be connected to the corresponding VFXI pin through a resistive network to set the transmit gain. Refer to Figure 5 for details. Voice Frequency Transmitter Input. This pin is the input to the gain setting amplifier in the transmit path. SLIC Signaling Output for Channel 3. SLIC Signaling Output for Channel 2.
O
I
O
O
2
I/O3_0
O2_4
O2_3
O2_2
O3_4
O3_3
O3_2
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Name O1_4 O1_3 O1_2 O0_4 O0_3 O0_2 I/O3_1 I/O3_0 I/O2_1 I/O2_0 I/O1_1 I/O1_0 I/O0_1 I/O0_0 DX VDD DR TSX FS MCLK BCLK CCLK CO CI CS GND CNF Type O O I/O I/O I/O I/O O -I O I I I I O I I -O Pin Number 35 34 33 30 29 28 12 13 7 8 32 31 27 26 14 15 16 17 18 19 20 21 22 23 24 25 36 Description SLIC Signaling Output for Channel 1. SLIC Signaling Output for Channel 0. SLIC Signaling I/O for Channel 3. SLIC Signaling I/O for Channel 2. SLIC Signaling I/O for Channel 1. SLIC Signaling I/O for Channel 0. Transmit PCM Data Output. PCM data is shifted out of DX on rising edges of BCLK. +5 V Digital Power Supply. All power supply pins should be connected to the power plane of the circuit board. Receive PCM Data Input. PCM data is shifted into DR on falling edges of BCLK. Time Slot Indicator Output, Open Drain This pin pulses low during the active time slot of each channel. A low level on this pin indicates active DX output. Frame Synchronization. The FS pulse serves as the reference to time slots. The width of the FS pulse should be at least one BCLK cycle. Master Clock. Master Clock provides the clock for DSP. It can be 2.048 MHz, 4.096 MHz or 8.192 MHz. It must be synchronous to FS. Bit Clock. Bit Clock shifts out PCM data on DX pin and shifts in PCM data on DR pin. The clock can vary from 512 kHz to 8.192 MHz at 64 kHz increment, depending on the time slot requirement of the system. Serial Control Interface Clock. This is the clock for Serial Control Interface. It can be up to 8.192 MHz. Serial Control Interface Data Tri-State Output. This pin is used to monitor SLIC working status. It is in high impedance state when CS is high. Serial Control Interface Data Input. Data input on this pin can control both CODEC and SLIC. Chip Select. A low level on this pin enables the Serial Control Interface. Ground. All ground pins should be connected to the ground plane of the circuit board. Capacitor For Noise Filter. This pin should be connected to GNDA via a 0.1 µF capacitor.
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IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT821034 contains four channel PCM CODEC with on chip digital filters. It provides the four-wire solution for the subscriber line circuitry in digital switches. The device converts analog voice signal into digital PCM samples, and converts digital PCM samples back to analog signal. Digital filters are used to bandlimit the voice signals during conversion. The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz or 8.192 MHz. Internal circuitry determines the master clock frequency automatically. Four channels of serial PCM data are time multiplexed via two pins, DX and DR. The time slots of the four channels can be programmed dynamically. The control words can be written by a microcontroller via the Serial Control Interface. Dynamic time-slot assignment can accommodate 8 to 128 time slots corresponding to the bit clock (BCLK) frequency from 512 kHz to 8.192 MHz. The IDT821034 offers two timing modes, delay mode and non-delay mode. Mode selection is done by programming the Configuration Register. The two modes are distinguished by time slot zero definition. In delay mode, the time slot zero is defined as starting on the first rising edge of BCLK after FS = `1' is detected by the falling edge of BCLK (Figure 7). While in non-delay mode, the time slot zero starts when both BCLK and FS are high (Figure 8). The device provides a programmable interface to SLIC (Subscriber Line Interface Circuit). Each channel of the IDT821034 has three output pins and two I/O pins for SLIC signaling. These interface pins are mapped to internal registers and are accessed by the microcontroller via the Serial Control Interface. In this way, the IDT821034 provides high level of integration in line card design. The Serial Control Interface of IDT821034 consists of four pins (CI, CO, CS and CCLK), as shown in Figure 1, for the communication to a microcontroller. Via this interface, the microcontroller can control the CODEC and SLIC working modes as well as monitor the SLIC status.
information retain the data in this mode. Each of the four channels in the IDT821034 can be in either normal mode or standby mode. The mode selection of each channel is done by the microcontroller via the Serial Control Interface. When in normal mode, each channel of the IDT821034 is able to transmit and receive both PCM and analog information. This is the operating mode when a telephone call is in progress. Gain Programming Transmit gain and receive gain of each channel in IDT821034 can be varied by programming DSP digital filter coefficients. Transmit gain can be varied within the range of -3 dB to +13 dB; while receive gain can be varied within the range of -13 dB to +3 dB. This function allows the
IDT821034 to be used with SLICs of different gain requirement.
O P E R A T I O N CONTROL
Gain programming coefficient can be written into IDT821034 via Serial Control Interface. The detailed operation will be covered in Serial Control Interface description. The gain programming coefficients should be calculated as: Transmit : Coeff_X = round [ gain_X0dB × gain_X ] Receive: Coeff_R = round [ gain_R0dB × gain_R ] where: gain_X0dB = 1820; gain_X is the target gain; Coeff_X should be in the range of 0 to 8192. gain_R0dB = 2506; gain_R is the target gain; Coeff_R should be in the range of 0 to 8192. A gain programming coefficient is 14-bit wide and in binary format. The 7 Most Significant Bits of the coefficient is called GA_MSB_Transmit for transmit path, or is called GA_MSB_Receive for receive path; The 7 Least Significant Bits of the coefficient is called GA_LSB_ Transmit for transmit path, or is called GA_LSB_Receive for receive path. An example is given below to clarify the calculation of the coefficient. To program a +3 dB gain in transmit path and a -3.5 dB gain in receive path:
Linear Code of +3 dB
The following operation description applies to all four channels of the IDT821034. Initial State The IDT821034 has a built-in power on reset circuit. After initial power up, the device defaults to the following mode: 1. A-law is selected; 2. Delay mode is selected; 3. I/O pins of SLIC interface are set to input mode; 4. SLIC Control and Status Register bits are set to `0'; 5. All four channels are placed in standby mode; 6. All transmit and receive time slots are disabled with Time Slot Registers set to zero; 7. DX is set to high impedance state. Operating Modes There are two operating modes for each transmit or receive channel: standby mode and normal mode. When the IDT821034 is first powered on, standby mode is the default mode. Microcontroller can also set the device into this mode via the Serial Control Interface. In standby mode, the Serial Control Interface remains active to receive commands from the microcontroller. All other circuits are powered down with the analog outputs placed in high impedance state. All circuits which contain programmed
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= 103/20 = 1.412537545 = round (1820 × 1.412537545) = 2571 = 0010100, 0001011 (in binary format ) = 0010100 = 0001011
Coeff_X
GA_MSB_Transmit GA_LSB_Transmit
Linear Code of -3.5 dB = 10(-3.5/20) = 0.668343917 Coeff_R = round (2506 × 0.668343917) = 1675 = 0001101, 0001011 (in binary format) = 0001101 = 0001011
GA_MSB_Receive GA_LSB_Receive
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
INDUSTRIAL TEMPERATURE RANGE
S I G N A L PROCESSING
High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) are used in the IDT821034 to provide the required conversion accuracy. The associated decimation and interpolation filters are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering and sample rate conversion. Transmit Signal Processing In the transmit path, the analog input signal is received with a gain setting amplifier. The signal gain is set by the resistive feedback network as shown in the application circuit (Figure 5). The output of the gain setting amplifier is connected internally to the input of the anti-alias filter for the oversampling ADC. The digital output of the oversampling ADC is decimated and sent to the DSP. The transmit filter is implemented in the DSP as a digital bandpass filter. The filtered signal is further decimated and compressed to PCM format. Transmit PCM Interface The transmit PCM interface clocks the PCM data out of DX pin on rising edges of BCLK according to the time slot assignment. The frame sync (FS) pulse identifies the beginning of a transmit frame, or time slot zero. The time slots for all channels are referenced to FS. The IDT821034 contains user programmable Transmit Time Slot Register for each transmit channel. The register is 7 bits wide and can accommodate up to 128 time slots (corresponding to the maximum BCLK frequency of 8.192 MHz) in each frame. The PCM Data is transmitted serially on DX pin with the Most Significant Bit (MSB), or Bit 7, first. When the device is first powered up, all transmit time slots are disabled with Transmit Time Slot Registers set to zero. DX pin remains in highimpedance state. To power up or power down each transmit channel, Configuration Register and the corresponding Time Slot Register must be programmed. Receive Signal Processing In the receive path, the PCM code is received at the rate of 8,000 samples per second. The PCM code is expanded and sent to the DSP for interpolation and receive channel filtering function. The receive filter is implemented in the DSP as a digital lowpass filter. The filtered signal is then sent to an oversampling DAC. The DAC output is post-filtered and then delivered at VFRO pin by a power amplifier. The amplifier can drive resistive load higher than 2 k. Receive PCM Interface The receive PCM interface clocks the PCM data into DR pin on falling edges of BCLK according to the time slot assignment. The receive time slot definition and programming is similar to that of the transmit time slot. The IDT821034 contains a user programmable Receive Time Slot Register for each receive channel. The register is 7 bits wide and can accommodate up to 128 time slots (corresponding to the maximum BCLK frequency of 8.192 MHz) in each frame. The PCM Data is received serially on DR pin with the MSB (Bit 7) first. When the device is first powered up, all receive time slots are disabled with Receive Time Slot Registers set to zero. Data on DR pin is ignored. To power up or power down each receive channel, Configuration Register and the corresponding Time Slot Register must be programmed.
Serial Control Interface A Serial Control Interface is provided for a microprocessor to access the control and status registers of IDT821034. The control registers include Configuration Register, Time Slot Registers, SLIC Control Registers and Gain Adjustment Registers. They are used to program the working modes of CODEC and SLIC. The status registers include SLIC Status Registers. They are used to monitor SLIC functions. All registers are 8 bits wide. The Serial Control Interface consists of CO, CI, CS and CCLK pins (see Figure 1). A microprocessor initiates a write or read cycle after low level is asserted on CS pin. In the microprocessor write cycle, 8 bits of serial data on CI pin are shifted into the device at falling edges of CCLK. In the microprocessor read cycle, 8 bits of serial data are shifted out of the device on CO pin at rising edges of CCLK. At the end of each 8-bit transaction, the microprocessor sets CS high to terminate the cycle. Multiple accesses to the device are separated by an idle state (high level) of CS. The width of CS high level is at least three CCLK cycles. The IDT821034 has a Configuration Register. Its register bits are designated CR.7 - CR.0. The definition of the bits in Configuration Register i s shown in Table 1. If the leading data bit on CI pin is `1' in a microprocessor write cycle, the 8-bit data on CI pin is latched into Configuration Register with MSB first. There are eight Time Slot Registers for four transmit channels and four receive channels. The definition of the bits in Time Slot Register is shown in Table 2. Since PCM sample rate is 8k samples/sec and each sample is 8 bits wide, each time slot occupies 64 kbits/sec of data rate. The number of time slots in a frame is equal to the ratio of the bit clock frequency (BCLK) to 64 kHz. For the maximum BCLK frequency of 8.192 MHz, the number of time slots in a frame is 8.192MHz/64kHz, or 128. The minimum number of time slots (corresponding to the minimum BCLK frequency of 512 kHz) in a frame is 8. The relationship between frequently used BCLK frequencies and the number of time slots in a frame is shown in Table 3. Bit 6-0 in each Time Slot Register identify the time slot number (0 to 127) of the corresponding transmit or receive channel. Time Slot Registers can be accessed by specifying the transmit/ receive select (CR.1 and CR.0) and channel address (CR.3 and CR.2) in Configuration Register. If CR.6 = `0' and the leading data bit on CI pin is `0' in a microprocessor write cycle, the 8-bit data on CI pin is latched into the selected Time Slot Register with MSB first. There are four SLIC Control Registers for four channel SLIC signaling control. The definition of the bits in a SLIC Control Register is shown in Table 4. SLIC Control Registers can be accessed by specifying the channel address (CR.3 and CR.2) in Configuration Register. If CR[6:4] = `101' and the leading data bit on CI pin is `0' in a microprocessor write or read cycle, the 8-bit data on CI pin is latched into the selected SLIC Control Register with MSB first. There are four SLIC Status Registers for four channel SLIC monitoring. The bits in each SLIC Status Register are mapped to the SLIC signaling output and I/O pins of the corresponding channel as shown in Table 5. It should be noted that the last 3 bits of the SLIC Status Register are always mapped to I/O1_0, I/O2_0 and I/O3_0. This feature allows a rapid read process of the SLIC status when Channel 0 is selected. The SLIC Status Registers can be accessed by specifying the channel address (CR.3 and CR.2) in the Configuration Register. If CR[6:4] = `101', as a result of the previous write to the Configuration Register, the subsequent microprocessor cycle is a read cycle. The content of the selected SLIC Status Register is shifted out of the device on CO pin with MSB first. There are 16 Gain Adjustment Registers for both transmit and r e c e i v e paths of four channels. For each path, there are two
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