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Details, datasheet, quote on part number:821064
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Datasheet text preview:
QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
FEATURES
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IDT821064
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4 channel CODEC with on-chip digital filters Software selectable compressed (A/µ-law) or linear code conversion Meets ITU-T G.711 - G.714 requirements Programmable digital filter adapting to system demands: - AC impedance matching - Transhybrid balance - Frequency response correction - Gain setting GCI (IOM-2) control interface Broadcast mode for coefficient setting 7 SLIC signaling pins (including 2 debounced pins) per channel Fast hardware ring trip mechanism Two programmable tone generators per channel for testing,
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ringing and DTMF generation FSK generator Two programmable chopper clocks Master clock frequency selectable: 2.048 MHz or 4.096 MHz Advanced test capabilities - 3 analog loop back tests - 5 digital loop back tests - Level metering function High analog driving capability (300 AC ) TTL and CMOS compatible digital I/O CODEC identification +5 V single power supply Low power consumption Operating temperature range: -40 °C to +85 °C Package available: 64 pin PQFP
FUNCTIONAL BLOCK DIAGRAM
CH1
VIN1 VOUT1 2 Inputs 3 I/Os 2 Outputs Filter and A/D D/A and Filter
CH3
Filter and A/D VIN3 VOUT3 2 Inputs 3 I/Os 2 Outputs
DSP CORE
D/A and Filter
SLIC Signaling
SLIC Signaling
CH2
MCLK CHCLK1 CHCLK2
CH4
PLL and Clock Generation
General Control Logic
PCM/GCI Interface
DD DU
RESET
S0
S1
FSC
DCL
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
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© 2003 Integrated Device Technology, Inc.
MARCH 14, 2003
DSC-6036/5
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT821064 is a feature rich, single-chip, programmable 4 chann e l PCM CODEC with on-chip filters. Besides the µ-Law/A-Law companding and linear coding/decoding (14 effective bits + 2 extra sign bits), IDT821064 also provides 1 FSK generator (can be used for sending Caller-ID messages), 2 programmable Tone generators per channel (which can also generate ring signals) together with 2 programmable chopper clocks for SLIC. The digital filters in IDT821064 provide the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. An integrated programmable DSP realizes AC Impedance Matching, Transhybrid Balance, Frequency Response Correction and Gain Setting functions. The device also provides 7
signaling pins to SLIC on per channel basis. The IDT821064 has a General Control Interface (GCI), which is also known as ISDN Oriented Module (IOM ®-2). The IDT821064 supports both compressed and linear data format. This function provides convenience for the VoXXX applications. The device also offers strong test capability with several analog/digital loopbacks and level metering function. It brings convenience to system maintenance and diagnosis. A unique feature of `Hardware Ring Trip' is implemented in IDT821064. When off-hook signal is detected, IDT821064 can reverse an output pin to stop ringing immediately. The IDT821064 can be used in Integrated Access Devices (IADs), i.e. VoIP and VoDSL.
PIN CONFIGURATIONS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SI2_2 SI1_2 SB3_2 SB2_2 SB1_2 SO2_2 SO1_2 SO1_1 SO2_1 SB1_1 SB2_1 SB3_1 SI1_1 SI2_1 NC CHCLK1
VIN1 GNDA1 VOUT1 VDDA12 VOUT2 GNDA2 VIN2 CNF VDDB VIN3 GNDA3 VOUT3 VDDA34 VOUT4 GNDA4 VIN4
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
IDT821064 64 pin PQFP
DCL FSC NCR NC NC DD DU NC VDDD RESET MCLK GNDD NC S1 S0 NCR
IOM ®-2 is a registered trademark of Siemens AG.
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SI2_3 SI1_3 SB3_3 SB2_3 SB1_3 SO2_3 SO1_3 SO1_4 SO2_4 SB1_4 SB2_4 SB3_4 SI1_4 SI2_4 NC CHCLK2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name GNDA1 GNDA2 GNDA3 GNDA4 GNDD VDDA12 VDDA34 VDDD VDDB CNF VIN1-4 VOUT1-4 SI1_(1-4) SI2_(1-4) SB1_(1-4) SB2_(1-4) SB3_(1-4) SO1_(1-4) SO2_(1-4) DU DD FSC DCL S0 S1 MCLK RESET CHCLK1 CHCLK2 NCR NC Type P P P P P I O I Pin Number 50 54 59 63 21 52 61 24 57 56 49, 55, 58, 64 51, 53, 60, 62 36, 47, 2, 13 35, 48, 1, 14 39, 44, 5, 10 38, 45, 4, 11 37, 46, 3, 12 41, 42, 7, 8 40, 43, 6, 9 26 27 31 32 18 19 22 23 33 16 17,30 15,20,25 28,29,34 Description Analog Ground. All ground pins should be connected together. Digital Ground. All digital signals are referred to this pin. +5V Analog Power Supply. These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. +5V Digital Power Supply. +5V Analog Power Supply. This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. Capacitor Noise Filter This pin should be connected to ground via a 0.22µF capacitor. Analog Voice Inputs. These pins should be connected to the SLIC via a capacitor (0.22 µF). Voice Frequency Receiver Outputs. These pins can drive 300 AC load. They can drive transformers directly. SLIC signalling Inputs with debounced function for Channel 1-4.
I/O
Bi-directional SLIC Signalling I/Os for Channel 1-4, can be programmed as Input or Output.
O O I I I I I I O O
SLIC Signalling Outputs for Channel 1-4. GCI Data Upstream GCI data is serially transmitted to this pin for all 4 channels of IDT821064. GCI Data Downstream GCI data is received serially from this pin for all 4 channels of IDT821064. Frame Sync. FSC is an 8 kHz signal that identifies the beginning of Timeslot 0 in the GCI frame. Data Clock. The data clock is either 2.048 MHz or 4.096 MHz, which is determined automatically by IDT821064. Time Slot Select These pins are used to select one of the four time slot positions for Voice channels, Monitor and C/I channels. Master Clock Input. Master clock provides the clock for DSP. It can be 2.048 MHz or 4.096 MHz, which is determined automatically by IDT821064. It is recommended to connect MCLK pin and DCL pin together. Reset Input. Forces the device to default state. Active low. Chopper Clock Output. Provides a programmable (2 -28 ms) output signal synchronous to MCLK. Chopper Clock Output. Provides a programmable 256 kHz, or 512 kHz or 16.384 MHz output signal synchronous to MCLK Recommend to be connected to GNDD. No connection
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IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT821064 is a four-channel PCM CODEC with on-chip digital filters. It provides the four-wire solution for the subscriber line circuitry in digital switches. The IDT821064 converts analog voice signals to digital PCM samples and digital PCM samples back to analog voice signals. Digital filters are used to bandlimit the voice signals during conversion. High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) in the IDT821064 provide the required conversion accuracy. The associated decimation and interpolation filters are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering, sample rate conversion and PCM companding. See the Functional Block Diagram. In the transmit path, the analog voice signal input from VIN pin is converted to PCM code by ADC, DSP and PCM companding circuits. Band-limiting functions as specified in ITU-T are implemented by digital filters. At last the fully processed signal is transferred to the GCI interface, in a compressed or linear signal presentation. In the receive path, the digital signal is received via the GCI interface. Then it is expanded and sent to the DSP for interpolation and receive c h a n n e l filtering function. The filtered signal is then sent to an oversampling DAC. The DAC output is post-filtered and then delivered at VOUT pin by a power amplifier. The amplifier can drive resistive load higher than 300 AC.
The Frame Sync (FSC) pulse identifies the beginning of the Transmit and Receive frames and all GCI time slots are referenced to it. The Data Clock (DCL) is either 2.048 MHz or 4.096MHz, the internal circuit of IDT821064 monitors this input to determine which frequency is being used. The internal timing will be adjusted according to the DCL frequency so that DU and DD operate at 2M rate. IDT821064 allows both compressed and linear data format coding/ decoding. VDS bit in Global Regiser 5 makes the selection of voice data format. COMPRESSED GCI MODE In GCI compressed mode, one GCI frame consists of 8 GCI time slots, the Data Upstream Interface transmits four 8-bit bytes per GCI time slot. They are: - Two voice data bytes from the A-law or µ-law compressor for two different channel, for easy description, we name the two channels as channel A and channel B. The compressed voice data bytes for channel A and B are 8-bit wide; - One Monitor channel byte, which is used for reading control data from the device for Channel A and B; - One C/I channel byte, which contains a 6 bit width C/I channel subbyte together with an MX bit and an MR bit. All real time signaling information is carried on the C/I channel sub-byte. The MX (Monitor Transmit) bit and MR (Monitor Receive) bit are used for handshaking functions for Channel A and B. Both MX and MR are active low. Transmit logic controls the transmission of data onto the GCI bus. The data structure of the Data Downstream is as same as that of Upstream. The Data Downstream Interface logic controls the reception of data bytes from the GCI bus. The two compressed voice channel data bytes of the GCI time slot are transferred to the A-law or µ-law expansion logic circuit. The expanded data is passed to the receive path of the signal processor. The Monitor Channel and C/I Channel bytes are transferred to the GCI control logic for processing. Figure 1 shows the overall compressed GCI frame structure.
GCI INTERFACE
The General Control Interface (GCI) provides communication of both control and voice data between the GCI highway and SLIC over a pair of pins on the IDT821064. The IDT821064 sends Data Upstream out of the DU pin and receives Data Downstream on the DD pin. DCL and FS are two input clock signals providing Data Clock (DCL) and Frame Synchronization (FS) information for the device. A complete GCI frame is sent upstream on DU pin and received downstream on DD pin every 125 µs.
125 µs FSC DCL DD DU Detail DD DU
Voice Channel A Voice Channel B Monitor Channel C/I Channel
MM RX MM RX
TS0 TS0
TS1 TS1
TS2 TS2
TS3 Detail TS3
TS4 TS4
TS5 TS5
TS6 TS6
TS7 TS7
Voice Channel A
Voice Channel B
Monitor Channel
C/I Channel
Figure 1. Compressed GCI Frame Structure
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IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
Table 1 - Time Slot Selection for Compressed GCI
IDT821064 Channels 1 2 3 4 S1=0,S0=0 Voice Time Slot Channel Time slot 0 A Time slot 0 B Time slot 1 A Time slot 1 B S1=0,S0=1 Voice Time Slot Channel Time slot 2 A Time slot 2 B Time slot 3 A Time slot 3 B S1=1,S0=0 Voice Time Slot Channel Time slot 4 A Time slot 4 B Time slot 5 A Time slot 5 B S1=1,S0=1 Voice Time Slot Channel Time slot 6 A Time slot 6 B Time slot 7 A Time slot 7 B
In compressed operation, two GCI time slots are required to access the four channels of IDT821064. The GCI time slot assignment is determined by S1 and S0 as shown in Table 1. LINEAR GCI MODE In GCI linear mode, one GCI frame consists of 8 GCI time slots, each GCI time slot consists of four 8-bits bytes. Four of the 8 GCI time slots are used as Monitor Channel and C/I octet, they have a common data structure: - Two don't_care bytes. - One Monitor Channel byte, which is used for reading/writing control data/coefficients from/to the device for Channel A and B. - One C/I byte, which contains a 6 bit width C/I channel sub-byte together with an MX bit and an MR bit. All real time signaling information is carried on the C/I channel sub-byte. The MX (Monitor Transmit) bit and MR
(Monitor Receive) bit are used for handshaking functions for Channel A and B. Both MX and MR bits are active low . Other four GCI time slots are used for linear voice data (a 16-bit 2's complement number, b15 and b14 are the same as b13, which is the sign bit, b13 to b0 are effective bits). Each GCI time slot consists of two 16-bit linear voice data bytes: one byte contains the linear voice data for Channel A, the other byte contains the linear voice data for Channel B. The GCI time slot assignment is determined by S1 and S0 pin. When S0 and S1 are both low, the linear GCI Frame Structure is shown in Figure 2. In linear operation, because one chip of the four-channel IDT821064 occupies four GCI time slots ( two for voice data and two for C/I and monitor), the rest four GCI time slots can be used by other device. There are four locations in the 8-time-slots GCI bus for one IDT821064 to select, see Table 2.
125 µs FSC DCL DD DU Detail A DD DU
TS0 Detail A TS0 TS1 TS1 TS2 Detail B TS2 TS3 TS4 TS5 TS6 TS7 TS3 TS4 TS5 TS6 TS7
TS0-1 for Monitor and C/I
Unused
TS2-3 for Linear Voice Data
Unused Monitor Channel C/I Channel
MM RX MM RX
Unused
Unused
Monitor Channel
C/I Channel
Detail B DD DU
16-bit Linear Voice Data for Channel A 16-bit Linear Voice Data for Channel B
16-bit Linear Voice Data for Channel A
16-bit Linear Voice Data for Channel B
Figure 2. Linear GCI Frame Structure
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