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Part: 821068
Category:
Description: Programmable Octal PCM Codec
Company: Integrated Device Technology, Inc.
Datasheet: Download 821068 datasheet File size : 78 kB
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OCTAL PROGRAMMABLE PCM CODEC
PRELIMINARY IDT821068
FEATURES
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8 channel CODEC with on-chip digital filters Programmable A/µ-law compressed or linear code conversion Meets ITU-T G.711 - G.714 requirements Programmable digital filter adapting to system demands: - AC impedance matching - Transhybrid balance - Frequency response correction - Gain setting Supports two programmable PCM buses and one GCI bus Flexible PCM interface with up to 128 programmable time slots, data rate from 512 kbits/s to 8.192 Mbits/s Broadcast mode for coefficient setting 7 SLIC signaling pins (including 2 debounced pins) per channel Fast hardware ring trip mechanism Two programmable tone generators per channel for testing, ringing and DTMF generation
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Programmable teletax signal generation (12 kHz or 16 kHz) FSK generator Two programmable chopper clocks Master clock frequency selectable: 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz Advanced test capabilities - 3 analog loopback tests - 5 digital loopback tests - Level metering function High analog driving capability (300 AC) TTL and CMOS compatible digital I/O CODEC identification +5 V single power supply Operating temperature range: - 40°C to + 85°C Package available: 128 pin PQFP
FUNCTIONAL BLOCK DIAGRAM
MPI INT RESET
CH1
VIN1 VOUT1 2 Inputs 2 I/Os 3 Outputs Filter and A/D D/A and Filter
General Control Logic
CH5
Filter and A/D D/A and Filter VIN5 VOUT5 2 Inputs 2 I/Os 3 Outputs
SLIC Signaling
SLIC Signaling
CH2 CH3
DSP Core
CH6 CH7
CH4
MCLK CHCLK1 CHCLK2
CH8
DR1/DD DR2 DX1/DU DX2
PLL and Clock Generation
Serial Interface
PCM/GCI Interface
CCLK /TS
The IDT logo is a registered trademark of Integrated Device Technology, Inc
CS
CI/ CO DOUBLE
FS BCLK TSX1 TSX2 / F S C /DCL
INDUSTRIAL TEMPERATURE RANGE
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©2003 Integrated Device Technology, Inc.
JANUARY 10, 2003
DSC-6033/6
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT821068 is a feature rich, single-chip, programmable 8 channel PCM CODEC with on-chip filters. Besides the A-Law/µ-Law companding and linear coding/decoding (16-bit 2's complement), IDT821068 provides 2 programmable Tone generators per channel (which can also generate ring signals), 1 FSK generator, 1 programmable Teletax Signal generator and 2 programmable chopper clocks for SLIC. The digital filters in IDT821068 provide the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. An integrated programmable DSP realizes AC Impedance Matching, Transhybrid Balance, Frequency Response Correction and Gain Setting functions. The IDT821068 supports 2 PCM buses with programmable sampling edge, that allows an extra delay of up to 7 clocks. Once the delay is determined, it is effective to
all eight channels of IDT821068. The device also provides 7 signaling pins to SLIC on per channel basis. T h e IDT821068 provides 2 programming interfaces: Microprocessor Interface (MPI) and General Control Interface (GCI), which is also known as ISDN Oriented Module (IOM ®-2). For both MPI and GCI programming, the device supports both compressed and linear data format. The device also offers strong test capability with several analog/ digital loopbacks and level metering function. It brings convenience to system maintenance and diagnosis. A unique feature of `Hardware Ring Trip' is implemented in IDT821068. When off-hook signal is detected, IDT821068 can reverse an output pin to stop ringing immediately. T h e IDT821068 can be used in digital telecommunication applications such as Central Office Switch, PBX, DLC and Integrated Access Device (IAD), i.e. VoIP and VoDSL.
PIN CONFIGURATIONS
SB2_5 SO1_5 SO2_5 SO3_5 GND56 MPI CS CCLK/TS CI/DOUBLE CO INT NC NC NC NC NC NC NC NC RESET NC GND12 SO3_1 SO2_1 SO1_1 SB2_1
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
SB1_5 SI2_5 SI1_5 VDD56 SO3_6 SO2_6 SO1_6 SB2_6 SB1_6 SI2_6 SI1_6 VDDAS CNF2 VOUT5 GNDA5 VIN5 VDDA56 VIN6 GNDA6 VOUT6 VOUT7 GNDA7 VIN7 VDDA78 VIN8 GNDA8 VOUT8 SI1_7 SI2_7 SB1_7 SB2_7 SO1_7 SO2_7 SO3_7 VDD78 SI1_8 SI2_8 SB1_8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
IDT821068 128 PIN PQFP
SB2_8 SO1_8 SO2_8 SO3_8 GND78 GNDDP NC CHCLK1 CHCLK2 VDDDP MCLK BCLK/DCL FS/FSC NC TSX2 DX2 DR2 TSX1 DX1/DU DR1/DD NC GND34 SO3_4 SO2_4 SO1_4 SB2_4
IOM ®-2 is a registered trademark of Siemens AG.
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SB1_1 SI2_1 SI1_1 VDD12 SO3_2 SO2_2 SO1_2 SB2_2 SB1_2 SI2_2 SI1_2 GNDAS CNF1 VOUT1 GNDA1 VIN1 VDDA12 VIN2 GNDA2 VOUT2 VOUT3 GNDA3 VIN3 VDDA34 VIN4 GNDA4 VOUT4 SI1_3 SI2_3 SB1_3 SB2_3 SO1_3 SO2_3 SO3_3 VDD34 SI1_4 SI2_4 SB1_4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 GNDA6 GNDA7 GNDA8 GNDAS GND12 GND34 GND56 GND78 GNDDP VDDA12 VDDA34 VDDA56 VDDA78 VDDAS VDD12 VDD34 VDD56 VDD78 VDDDP VIN1-8 VOUT1-8 SI1_(1-8) SI2_(1-8) SB1_(1-8) SB2_(1-8) SO1_(1-8) SO2_(1-8) SO3_(1-8) O I Type Pin Number 15 19 22 26 88 84 81 77 12 124 43 107 60 59 17 24 86 79 91 4 35 99 68 55 16, 18, 23, 25 87, 85, 80, 78 14, 20, 21, 27 89, 83, 82, 76 3, 11, 28, 36 100, 92, 75,67 2, 10, 29, 37 101, 93, 74,66 1, 9, 30, 38 102, 94, 73,65 128, 8, 31,39 103, 95,72, 64 127, 7, 32,40 104, 96,71, 63 126, 6, 33,41 105, 97,70, 62 125, 5, 34,42 106, 98,69, 61 46 Description
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Analog Ground. All ground pins should be connected together.
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Analog Ground For Bias. All ground pins should be connected together. Digital Ground. All ground pins should be connected together. Digital Ground For PLL. All ground pins should be connected together. +5V Analog Power Supply. These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. +5V Analog Power Supply For Bias. This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. +5V Digital Power Supply. These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. +5V Digital Power Supply For PLL. This pin should be connected to ground via a 0.1 µF capacitance. All power supply pins should be connected together. Analog Voice Inputs. These pins should be connected with the SLIC via a capacitor (0.22 µF). Voice Frequency Receiver Outputs. These pins can drive 300 AC load. It allows the direct driving of transformer. Debounced SLIC Signaling Inputs for Channel 1-8.
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I O
I/O
SLIC Signaling I/Os for Channel 1-8.
SLIC Signaling Outputs for Channel 1-8.
DX1/DU
O
DX2
O
49
DR1/DD
I
45
Transmit PCM Data Output (For MPI)/GCI Data Upstream (For GCI). In MPI mode, this pin remains high-impedance until a pulse appears on FS input. PCM data can output from DX1 or DX2 as selected by serial port, following the BCLK. In GCI mode, GCI data is serially transmitted on this pin for all 8 channels of IDT821068. Which part of the GCI data will be occupied is determined by CCLK/TS pin. Transmit PCM Data Output (For MPI). This pin remains high-impedance until a pulse appears on FS input. PCM data can output from DX1 or DX2 as selected by serial port. This pin is not used in GCI mode. Receive PCM Data Input (For MPI)/GCI Data Downstream (For GCI). In MPI mode, PCM data is shifted into DR1 or DR2 following the BCLK. PCM data can input from DR1 and DR2 as selected by serial port. In GCI mode, GCI data is received serially on this pin for all 8 channels of IDT821068. Which part of the GCI data will be transmitted is determined by CCLK/TS pin. 3
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Name DR2 Type I Pin Number 48 Description Receive PCM Data Input (For MPI). PCM data is shifted into DR1 or DR2 following the BCLK. PCM data can input from DR1 and DR2 as selected by serial port. This pin is not used in GCI mode Frame Synchronization signal (For MPI)/Frame Sync signal (For GCI). In MPI mode, FS is an 8 kHz synchronization clock that identifies the beginning of the PCM frame. In GCI mode, FSC is an 8 kHz signal that identifies the beginning of Timeslot 0 in the GCI frame. Bit Clock (For MPI)/Data Clock (For GCI). In MPI mode, BCLK pin clocks out the PCM data on DX1 or DX2 pin and clock in PCM data from DR1 or DR2 pin. It may vary from 512kHz to 8.192 MHz, and is required to be synchronous with FS. In GCI mode, DCL pin is either 2.048 MHz or 4.096 MHz. The frequency is selected by CI/DOUBLE pin. When CI/DOUBLE pin is low, DCL will be 2.048 MHz; when CI/DOUBLE pin is high, DCL will be 4.096 MHz. It is recommended to connect MCLK and DCL pin together. Timeslot Indicator Output (For MPI). This pin pulses low during the receive timeslot. A low on this pin indicates DX1/DX2 output. These two open-drain pins are not used in GCI mode. Chip Selection. In MPI mode, a low level on this pin enables the Serial Control Interface. In GCI mode, a low level on this pin configures a Compressed GCI operation, while a high level on this pin configures a Linear GCI operation. Serial Control Interface Data Input (For MPI)/Double DCL (For GCI). In MPI mode, data input on this pin can control both CODEC and SLIC. In GCI mode, this pin is used to determine the frequency of DCL. When low, DCL will be 2.048 MHz; when high, DCL will be 4.096 MHz. Serial Control Interface Data Tri-State Output (For MPI). This pin is used to monitor SLIC working status. It is in high impedance state when CS is high. This pin is not used in GCI mode. Serial Control Interface Clock (For MPI)/Timeslot Selection (For GCI). In MPI mode, this is the clock for Serial Control Interface. It can be up to 8.192 MHz. In Compressed GCI mode, this pin indicates which half of 8 continuous GCI timeslots is used. When this pin is low, timeslots 0-3 are selected; when this pin is high, timeslots 4-7 are selected. In Linear GCI mode, this pin indicates which half of 8 continuous GCI timeslots is used for voice signal. When this pin is low, timeslots 0-3 are used as Monitor channel and C/I octet, timeslots 4-7 are used for linear voice; when this pin is high, timeslots 4-7 are used for linear voice, timeslots 0-3 are used as Monitor channel and C/I octet. MPI/GCI Select. This pin is used to determine which operation mode the IDT821068 works in. When this pin is low, MPI/PCM mode is selected; When this pin is high, GCI mode is selected. Reset Input. Forces the device to default mode. Active low. Interrupt Output Pin. Active low interrupt signal for ch1-ch8, open-drain. It reflects the changes on SLIC pins. Master Clock. Master clock provides the clock for DSP. In MPI mode, it can be 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHZ, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz. It can be asynchronous to BCLK. In GCI mode, it is recommended to connect MCLK and DCL pin together. The frequency of MCLK can be 2.048 MHz or 4.096 MHz. See BCLK/DCL pin description. Chopper Clock Output. Provides a programmable (2 -28 ms) output signal synchronous to MCLK. Chopper Clock Output. Provides a programmable 256 kHz, or 512 kHz or 16.384 MHz output signal synchronous to MCLK. Capacitor Noise Filter. No Connection.
FS/FSC
I
52
BCLK/DCL
I
53
TSX1 TSX2
O
47 50
CS
I
109
CI/DOUBLE
I
111
CO
O
112
CCLK/TS
I
110
MPI RESET INT
I I O
108 122 113
MCLK
I
54
CHCLK1 CHCLK2 CNF1 CNF2 NC
O O -
57 56 13 90 44, 51, 58, 114 115,116,117,118 119,120,121,123
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IDT821068 OCTAL PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT821068 performs the CODEC/filter functions required for the s u b s c r i b e line interface circuitry in telecommunications system. IDT821068 converts analog voice signals to digital PCM samples and digital PCM samples back to analog voice signals. High performance o v e r s a m p l i n g Analog-to-Digital Converters (ADC) and Digital-toAnalog Converters (DAC) in the IDT821068 provide the required conversion accuracy. The associated decimation and interpolation filters are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering, sample rate conversion and PCM companding. See the Functional Block Diagram for more detail.
MPI/PCM MODE AND GCI MODE
Microprocessor Interface (MPI) and General Control Interface (GCI) help the user to program and control the CODEC. MPI pin selects the interface: `0' selects MPI mode and `1' selects GCI mode. MPI CONTROL MODE In MPI mode, the internal configuration registers (local/global), the SLIC signaling interface and the Coefficient-RAM, FSK-RAM of the IDT821068 are programmed by microprocessor via the serial control interface, which consists of four lines (pins): CCLK, CS, CI and CO. All the commands and data transmitted or received are aligned in byte (8 bits). CCLK is the Serial Control Interface Clock, it can be up to 8.192 MHz; CS is the Chip Select pin, a low level on it enables the serial control interface; CI and CO are the serial control interface data input and output, carrying the control commands and data bytes to/from the IDT821068. The data transfer is synchronized to the CCLK input. The contents of CI is latched on the rising edges of CCLK, while CO changes on the falling edges of CCLK. When finishing a read or write command, the CLCK must last at least one cycle after the CS is set high. During the e x e c u t i o n of commands that are followed by output data (read commands), the device will not accept any new commands from CI. The data transfer sequence can be interrupted by setting CS high. See Figure 1 and Figure 2. C C L K is the only reference of CI and CO pins. Its duty and frequency may not necessarily be standard.
PCM BUS In MPI mode, IDT821068 provides two flexible PCM buses for all 8 channels. The digital PCM data can be compressed (A/µ-law) or linear format, which is determined by the DMS bit in Global Command 7. The data rate can be configured as same as Bit Clock (BCLK) or half of it. The data can be transmitted or received either on BCLK rising edges or on falling edges. The data transmit and receive time slots can be offset from Frame Synchronization (FS) by 0 BCLK p e r i o d to 7 BCLK periods. See Figure 3. All the selections are implemented by Global Command 7, which is configured for all 8 channels. The PCM data of each channel can be assigned to any time slot of the PCM bus. The number of available time slots is determined by BCLK frequency. For example, when BCLK is 512 kHz, time slot 0-7 are available; when BCLK is 1.024 MHz, time slot 0-15 are available; w h e n BCLK is 8.192 MHz, time slot 0-127 are available. The IDT821068 allows any BCLK frequency between 512 kHz and 8.192 MHz at increment of 64 kHz in a system. When compressed format (8-bit) is selected, the voice data of one channel occupies one time slot. The TT[6:0] bits in Local Command 7 selects the transmit time slot for each channel, while the RT[6:0] bits in Local Command 8 selects the receive time slot for each channel. W h e n linear format is selected, the voice data is a 16-bit 2's complement number (b15 and b14 are the same as b13, which is the sign bit, b13 to b0 are effective bits). Then the voice data of one channel occupies a time slot group, which is consisted of 2 successive time slots. The TT[6:0] bits in Local Command 7 select the transmit time slot group for each channel, while the RT[6:0] bits in Local Command 8 select the receive time slot group for each channel. PCM data for each individual channel can be clocked out of DX1 or DX2 pin on the programmed edges of BCLK according to time slot assignment. The transmit highway (DX1/2) is selected by the THS bit in Local Command 7. The frame sync (FS) pulse identifies the beginning of a transmit frame, or time slot 0. The PCM data is transmitted serially on DX1 or DX2 with MSB first. PCM data for each channel can be clocked into DR1 or DR2 pin on the programmed edges of BCLK according to time slot assignment. The receive highway (DR1/2) is selected by the RHS bit in Local Command 8. The frame sync (FS) pulse identifies the beginning of a receive frame, or time slot 0. The PCM data is received serially from DR1 or DR2 with MSB first.
CCLK CS CI CO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Command Byte High 'Z'
Data Byte 1
Data Byte 2
Figure 1. An Example of Serial Interface Write Mode
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Others parts begin by 82
82-1 82-2
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