Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel® STbus, AT&T ® CHI and MVIP bus, supporting data rates up to four links can be byte interleaved on one system bus without external logic Provides up to three internal floating HDLC controllers for each framer to support ISDN PRI and V5.X interface. Each HDLC contains 128-byte deep FIFOs in both the receive and transmit directions Provides jitter attenuation performance exceeding the requirements set by the associated standards for both Rx and Tx path Provides payload, line and digital loop-backs Provides a floating Pseudo Random Bit Sequence / repetitive pattern generator/detector, which can be assigned to any one of eight framers, the pattern may be inserted / detected in an unframed Nx56K (T1 only) basis Provides signaling insertion / extraction for CCS / CAS and RBS signaling system Provides programmable codes insertion, data / sign inversion and digital milliwatt code insertion on a per channel / timeslot basis Supports automatic / manual alarming transmit and integration Provides performance monitor to counter CRC error, framing bit error, far end block CRC error (E1), out of frame event (T1/J1) and change of frame alignment event (T1/J1) Provides programmable In-band Loop-back Code transmitter/receiver, Bit Oriented Message generator / detector Supports polled or interrupt driven processing for all events Supports multiplexed or non-multiplexed address/data bus MPU interface for configuration, control and status monitoring JTAG boundary scan meets IEEE 1149.1 Low power 3.3V CMOS technology with 5V tolerant inputs Operating industrial temperature range: to +85°C Package available: 128 pin PQFP 144 pin PBGA

High density internet / J1 interface for routers, multiplexers, switches and digital modems. Frame relay switches and access devices (FRADS) SONET / SDH add drop multiplexers Digital private branch exchanges (PBX) Channel service units (CSU) and data service units (DSU) Channel banks and multiplexers Digital access and cross-connect systems (DACS)

E1 MODE: ITU-T: O.152, O.153; ETSI: ETS 300 011, ETS 300 233, ETS 324-1, ETS 347-1, TBR 4, TBR 12, TBR GO - MVIP T1/J1 MODE: ANSI: T1.403, T1.408; TR: TSY-000312, TSY-000499; AT&T: TR 62411 TTC: JT-G 703, JT-G 704, JT-G706, JT-G 1431

The is a flexible feature-rich octal T1/E1/J1 Framer. Controlled by the software, the IDT82V2108 can be globally configured as an Octal or T1/J1 Framer. When or T1/J1 has been set globally, the operation mode of each of the eight framers can be configured independently. The configuration is performed through a parallel Multiplexed/Non-Multiplexed microprocessor interface. The IDT82V2108 realizes frame synchronization, frame generating, signaling extraction and insertion, alarm and test signals generation and detection in a single chip. It also integrates up to three HDLC receivers and HDLC transmitters for each of the eight framers. In E1 Mode, the receive path of each framer can be configured to frame to Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be bypassed (unframed mode). It detects and indicates the event of out of Basic Frame Sync, out of CRC MultiFrame, out of Signaling Multi-Frame, the Remote Alarm Indication signal and the Remote Signaling Multi-Frame Alarm Indication signal. It also monitors the Red and AIS alarms. Basic Frame Alignment Signal errors, Far End Block Errors (FEBE) and CRC errors are counted. Up to three HDLC links are provided to extract the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. An Elastic Store Buffer that optionally supports slip buffering and adaptation to backplane timing is provided. In E1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, trunk conditioning, data inversion and pattern generation or detection are also supported on a per-timeslot basis. In E1 mode, the transmit path of each framer can be configured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be disabled (unframed mode). It can also transmit Remote Alarm Indication signal, the Remote Signaling Multi-Frame Alarm Indication signal, AIS signal and FEBE. Up to three HDLC links are provided to insert the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-timeslot basis. In E1 mode, any four of the eight framers can be multiplexed or demultiplexed to or from one of the two 8.192M bit/s buses. In T1/J1 mode, the receive path of each framer can be configured to frame to Super Frame (SF) or Extended Super Frame (ESF) formats. The framing can also be bypassed (unframed mode). It detects and indicates the out of SF/ESF sync event, the Yellow, Red and AIS alarms. It also detects the presence of inband loopback codes, bit oriented message. Frame Alignment Signal errors, CRC-6 errors, out of SF/ESF events and Frame Alignment position changes are counted. Up to two HDLC links are provides to extract the HDLC message on the Fbit or any arbitrary channels in ESF mode. An Elastic Store Buffer that optionally supports controlled slip and adaptation to backplane timing is provided. In T1/J1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, idle code insertion, data inversion and pattern generation or detection are also supported on a per-channel basis. In T1/J1 mode, the transmit path of each framer can be configured to generates SF or ESF. The framing can also be disabled (unframed mode). It can also transmit Yellow signal and AIS signal. Inband loopback codes and bit oriented message can also be transmitted. Up to two HDLC links are provided to insert the HDLC message on the F-

bit or any arbitrary channels in ESF mode. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-channel basis. In T1/J1 mode, the data stream of 1.544M bit/s can be converted to/ from the data stream of 2.048M bit/s on the system side by software configuration. In addition, any four of the eight framers can be multiplexed or de-multiplexed to or from one of the two 8.192M bit/s buses.

TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS MTSSIG[1:2] MTSD[1:2] TSFSn/ TSSIGn TSDn Transmit Clock Transmit System Interface

Inband Bit-Oriented Loopback HDLC #3 Message Code Transmitter #2 (E1 Transmitter Generator #1 only) (T1/J1 only) (T1/J1 only) Payload Loopback PRBS Generator /Detector Bit-Oriented Message Receiver (T1/J1 only)

Alarm #3 HDLC Detector Receiver (E1 (T1/J1 only) MRSSIG[1:2] MRSFS[1:2] RSCCK/ MRSCCK RSCFS/ MRSCFS RSDn RSCKn/ RSSIGn RSFSn Receive System Interface Receive Payload Control Receive CAS/RBS Buffer Elastic Store Buffer