A, B, and C grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: ­ VOH = 3.3V (typ.) ­ VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in SOIC, SSOP, and QSOP packages

The an 8-bit registered transceiver built using an advanced dual metal CMOS technology. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA.

Symbol VTERM(2) Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max to +120 Unit °C mA TSTG IOUT

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by =0.5V unless otherwise noted. 2. All device terminals.

Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF

NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = No Change = LOW-to-HIGH Transition

Name A0-7 B0-7 CPA CEA OEB CPB CEB OEA I/O Description Eight bidirectional lines carrying the A Register inputs or B Register outputs. Eight bidirectional lines carrying the B Register inputs or A Register outputs. Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions. Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When OEB is HIGH, the B0-7 outputs are in the high-impedance state. Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions. Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When OEA is HIGH, the A0-7 outputs are in the high-impedance state.

Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State Output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VCC = Min., IIN = ­18mA VCC = Max., VIN = GND or VCC = 0.5V Min. 200 0.01 Max. Unit mV µA

VOH VOL IOS IOFF Output HIGH Voltage Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Max., = GND(3) VCC = Max., VIN VO 4.5V IOH = ­8mA IOH = ­15mA IOL mA µA

NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter ­55°C. 5. This parameter is guaranteed but not tested.