|Description||HIGH Performance CMOS BUS Interface Register|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download IDT54FCT138CEB datasheet
|Cross ref.||Similar parts: CY54FCT138T, SN54AHCT138, SN54ALS138A, SN54F138, SN54HCT138, SN54LS138, SN54LS138-SP|
Equivalent to AMD's Am29823 bipolar registers in pinout/ function, speed, and output drive over full temperature and voltage supply extremes IDT54/74FCT823A equivalent to FASTTM speed IDT54FCT823B 25% faster than FAST IDT74FCT823C 40% faster than FAST Buffered common Clock Enable (EN) and Asynchronous Clear Input (CLR) IOL = 48mA (commercial) and 32mA (military) Clamp diodes on all inputs for ringing suppression CMOS power levels (1mW typ. static) TTL input and output compatibility CMOS output level compatible Substantially lower input current levels than AMD's bilopar Am29800 series (5µA max.) MIlitary product compliant to MIL-STD-883, Class B Available in the following packages: Commercial: SOIC Military: CERDIP, LCC
The FCT823 series is built using an advanced dual metal CMOS technology. The FCT823 bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The a 9-bit wide buffered register with Clock Enable (EN) and Clear (CLR) ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823 high-performance interface family is designed for highcapacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Symbol VTERM(3) TA TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature under BIAS Storage Temperature Power Dissipation DC Output Current 0.5 to VCC 0.5 to VCC V Commercial to +7 Military to +7 Unit V
Pin Name Dx CLR I/O I Description D flip-flop data inputs For both inverting and non-inverting registers, when the clear input is LOW and OE is LOW, the Qx outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-to-HIGH transition. Register 3-state outputs Clock Enable. When the clock enable is LOW, data on the DI input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Yx outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Yx outputs.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminals only. 3. Output and I/O terminals only.
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pFNOTE: 1. This parameter is measured at characterization but not tested.
Inputs OE CLR Dx CP Internal/ Outputs Z NC Function High Z Clear Hold Load
NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: to +70°C, VCC 5.0V ±5%, Military: to +125°C, VCC 5.0V ±10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VOH Off State (High Impedance) Output Current Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Max. Parameter Input HIGH Level Input LOW Level Input HIGH Current VCC = Max. Input LOW Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VI = VCC VI = GND VO = VCC VO = GND GND(3)
VCC = Min., IIN = 18mA VCC = Max., VO = VCC = 3V, VIN = VLC or VHC, IOH = 32µA VCC = Min IOH = 300µA VIN = VIH or VIL IOH = 15mA MIL IOH = 24mA COM'L VCC = 3V, VIN = VLC or VHC, IOL = 300µA VCC = Min IOL = 300µA VIN = VIH or VIL IOL = 32mA MIL IOL = 48mA COM'L
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not ttested.
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