|Category||Logic => Bus Interface => Bus Oriented Circuits|
|Title||Bus Oriented Circuits|
|Description||Fast CMOS 12-bit Tri-port Bus Exchanger|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download IDT54FCT162260ATEB datasheet
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1µA (max.) ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC 5V ±10% Balanced Output Drivers (±24mA) Reduced system switching noise Typical VOLP (Output Ground Bounce) 0.6V at VCC = 25°C Available in SSOP and TSSOP packages
The FCT162260T Tri-Port Bus Exchangers are high-speed 12-bit latched bus multiplexers/transceivers for use in high-speed microprocessor applications. These Bus Exchangers support memory interleaving with latched outputs on the B ports and address multiplexing with latched inputs on the B ports. The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The latch enable LE2B, LEA1B and LEA2B) inputs control data storage. When a latch-enable input is high, the latch is transparent. When a latch-enable input is low, the data at the input is latched and remains latched until the latch enable input is returned high. Independent output enables (OE1B and OE2B) allow reading from one port while writing to the other port. The FCT162260T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors.The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max to +120 Unit °C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 Max. 6 8 Unit pFNOTE: 1. This parameter is measured at characterization but not tested.
Signal LE1B LE2B SEL OEA OE1B OE2B I/O Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus. Bidirectional Data Port 1B. Connected to the even path or even bank of memory. Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory. Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B-Port is latched on the HIGH to LOW transition of LE1B Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the A-Port is latched on the HIGH to LOW transition or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW). Output Enable for 1B Port (Active LOW). Output Enable for 2B Port (Active LOW).
NOTES: 1. Output level before the indicated steady-state input conditions were established. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
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