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Part: IDT54FCT2533ATDB
Category:
Logic
Description: Fast CMOS Octal Transparent Latches
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT54FCT2533ATDB datasheet File size : 239 kB
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Datasheet text preview:
Integrated Device Technology, Inc.
FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT IDT54/74FCT533T/AT/CT IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FEATURES:
· Common features: Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages · Features for FCT373T/FCT533T/FCT573T: Std., A, C and D speed grades High drive outputs (-15mA IOH, 48mA IOL) Power off disable outputs permit "live insertion" · Features for FCT2373T/FCT2573T: Std., A and C speed grades Resistor output (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.)
Reduced system switching noise
DESCRIPTION:
T h e FCT373T/FCT2373T, FCT533T and FCT573T/ FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high- impedance state. The FCT2373T and FCT2573T have balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall timesreducing the need for external series terminating resistors. The FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
2564 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T
D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
2564 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-4216/6
6.12
1
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373/2373T
OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
2564 cnv* 03
32 D1 O1 O2 D2 D3 4 5 6 7 8
1
20 19 18 17 16 15 14
V CC O7
OE
O0
INDEX
D0
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
O3 GND
LE
O4
D4
2564 cnv* 04
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT573/2573T
OE VCC
1
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
2564 cnv* 05
D1
32 D2 D3 D4 D5 D6 4 5 6 7 8
20 19 18 17 16 15 14
O0
D0
INDEX
O1 O2 O3 O4 O5
L20-2
9 10 11 12 13
D7 GND
LE
O7
O6
2564 cnv* 06
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT533
OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 & E20-1 20 19 18 17 16 15 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
2564 cnv* 07
32 D1 O1 O2 D2 D3 4 5 6 7 8
1
20 19 18 17 16 15 14
VCC O7
OE
D0
O0
INDEX
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
LE O3 GND O4 D4
2564 cnv* 08
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
6.12
2
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (533)(1)
DN H L X Inputs LE H H X Outputs
FUNCTION TABLE (373 and 573)(1)
OE
L L H
ON
L H Z
2564 tbl 01
DN H L X
Inputs LE H H X
OE
L L H
Outputs ON H L Z
2564 tbl 02
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
DEFINITION OF FUNCTIONAL TERMS
Pin Names DN LE Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Complementary 3-State Outputs
2564 tbll 03
OE
ON
ON
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage 0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage 0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature 55 to +125 Under Bias TSTG Storage 55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current 60 to +120 Military 0.5 to +7.0 Unit V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2564 lnk 05
0.5 to VCC +0.5 55 to +125 65 to +135 65 to +150 0.5 60 to +120
V
°C °C °C
W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2564 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
6.12
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