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Details, datasheet, quote on part number:IDT54FCT377ATSOB
 
 
Part:IDT54FCT377ATSOB
Category:Logic => Flip-Flops => CMOS/BiCMOS->FCT/FCT-T Family
Description:Fast CMOS Octal D Flip-flop With Clock Enable
Company:Integrated Device Technology, Inc.
Datasheet:Download IDT54FCT377ATSOB datasheet   File size : 98 kB
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Datasheet text preview:
IDT54/74FCT377T/AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
FEATURES:
· · · ·
IDT54/74FCT377T/AT/CT/DT
· · · · ·
Std., A, C, and D grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: ­ VOH = 3.3V (typ.) ­ VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: ­ Industrial: SOIC, SSOP, QSOP ­ Military: CERDIP, LCC
DESCRIPTION:
The IDT54/74FCT377T is an octal D flip-flop built using an advanced dual metal CMOS technology. The IDT54/74FCT377T has eight edgetriggered, D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is low. The register is fully edge-triggered. The state of each D input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flop's O output. The CE input must be stable only one set-up time prior to the low-to-high transition for predictable operation.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D
3
D4
D
5
D6
D
7
CE
D CP CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
O0
O1
O2
O3
O4
O5
O6
O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-2630/8
© 2002 Integrated Device Technology, Inc.
IDT54/74FCT377T/AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
CE
O0
O0 D0 D1 O1 O2 D2 D3 O3 GND
2 3 4 5 6 7 8 9 10
19 18 17 16 15 14 13 12 11
O7 D7 D6 O6 O5 D5 D4 O4
O3 O4
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
D1 O1 O2 D2 D3
D0
INDEX
O7
CE
1
20
VCC
VCC
4 5 6 7 8
D7 D6 O6 O5 D5
CP
CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW
LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max ­0.5 to +7 ­0.5 to VCC+0.5 ­65 to +150 ­60 to +120 Unit V V °C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current
PIN DESCRIPTION
Pin Names D0 ­ D7 CE O0 ­ O7 CP Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input Description
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2 . Inputs and Vcc terminals only. 3 . Output and I/O terminals only.
FUNCTION TABLE(1)
Inputs Operating Mode Load "1" Load "0" Hold CP H CE l l h H D h l X X Outputs O H L No Change No Change
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1 . This parameter is measured at characterization but not tested.
NOTE: 1. H = h= L= l= X= =
HIGH Voltage Level HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition LOW Voltage Level LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition Don't Care LOW-to-HIGH Clock Transition
2
GND
CP
D4
IDT54/74FCT377T/AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial : TA = ­40°C to +85°C, VCC = 5.0V ± 5%; Military: TA = ­55°C to +125°C, VCC = 5.0V ± 10%
Symbol VIH VIL IIH IIL II VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input HIGH Current
(4)
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VCC = Min., IN = ­18mA VCC = Max. , VO = GND VCC = Min. VIN = VIH or VIL IOH = ­6mA MIL. IOH = ­8mA IND. IOH = ­12mA MIL. IOH = ­15mA IND.
(3)
Min. 2 --
Typ. (2) -- -- -- -- -- ­0.7 ­120 3.3 3 0.3 -- 200 0.01
Max. -- 0.8 ±1 ±1 ±1 ­1.2 ­225 -- -- 0.5 ±1 -- 1
Unit V V µA µA µA V mA V V V µA mV mA
VI = 2.7V VI = 0.5V
-- -- -- -- ­60 2.4 2 -- --
Input LOW Current(4)
(4)
Clamp Diode Voltage Short Circuit Current Output HIGH Voltage
VOL IOFF VH ICC
Output LOW Voltage Input/Output Power Off Leakage
(5)
VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO - 4.5V -- VCC = Max. VIN = GND or VCC
IOL = 32mA MIL. IOL = 48mA IND.
Input Hysteresis Quiescent Power Supply Current
-- --
NOTES: 1 . For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2 . Typical values are at VCC = 5.0V, +25°C ambient. 3 . Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4 . The test limit for this parameter is ±5µA at TA = -55°C. 5 . This parameter is guaranted but not tested.
3