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Part: IDT54FCT534CSO
Category:
Logic
Description: Fast CMOS Octal D Registers ( 3-state )
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT54FCT534CSO datasheet File size : 239 kB
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Datasheet text preview:
®
FAST CMOS OCTAL D REGISTERS (3-STATE)
IDT54/74FCT374/A/C IDT54/74FCT534/A/C IDT54/74FCT574/A/C
Integrated Device Technology, Inc.
FEATURES:
· IDT54/74FCT374/534/574 equivalent to FASTTM speed and drive · IDT54/74FCT374A/534A/574A up to 30% faster than FAST · IDT54/74FCT374C/534C/574C up to 50% faster than FAST · IOL = 48mA (commercial) and 32mA (military) · CMOS power levels (1mW typ. static) · Edge triggered master/slave, D-type flip-flops · Buffered common clock and buffered common threestate control · Product available in Radiation Tolerant and Radiation Enhanced versions · Military product compliant to MIL-STD-883, Class B · Meets or exceeds JEDEC Standard 18 specifications
DESCRIPTION:
The IDT54/74FCT374/A/C, IDT54/74FCT534/A/C and IDT54/74FCT574/A/C are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight D-type flip-flops with a buffered common clock and buffered 3-state output control. When the output enable (OE) is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the O outputs on the LOW-toHIGH transition of the clock input. The IDT54/74FCT374/A/C and IDT54/74FCT574/A/ C have non-inverting outputs with respect to the data at the D inputs. The IDT54/74FCT534/A/C have inverting outputs.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574
D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7
OE O0 O1 O2 O3 O4 O5 O6 O7
2603 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7
OE O0 O1 O2 O3 O4 O5 O6 O7
2603 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
MAY 1992
DSC-4622/2
7.13
1
IDT54/74FCT374/534/574/A/C FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT374
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
D0
3
2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 & E20-1
19 18 17 16 15 14 13 12 11
O7 D7 D6 O6 O5 D5 D4 O4 CP
2603 cnv* 03
O0
2
1
20
VCC
OE VCC O7
1 20 19 18 17 16 15 14
INDEX
D1 O1 O2 D2 D3
4 5 6 7 8
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
GND
CP
O3
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 & E20-1
20 19 18 17 16 15 14 13 12 11
VCC O0 O1 O2 O3 O4 O5 O6 O7 CP
2603 cnv* 05
32 D2 D3 D4 D5 D6 4 5 6 7 8
D0
OE
1
21 1 1 1 1 1 O1 O2 O3 O4 O5
L20-2
91 1 1 1
D7 GND
CP
O7
O6
VCC O0
IDT54/74FCT574
D1
INDEX
O4
D4
2603 cnv* 04
2603 cnv* 06
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT534
OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 P20-1 17 D20-1 16 SO20-2 15 & E20-1 14 13 12 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
2603 cnv* 07
32 D1 O1 O2 D2 D3 4 5 6 7 8
1
20 19 18 17 16 15 14
VCC O7
OE
O0
D0
INDEX
D7 D6 O6 O5 D5
L20-2
9 10 11 12 13
O3 GND
CP O4
D4
2603 cnv* 08
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
7.13
2
IDT54/74FCT374/534/574/A/C FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names DN CP ON Description D flip-flop data inputs. Clock Pulse for the register. Enters data on LOW-to-HIGH transition. 3-state outputs, (true). 3-state outputs, (inverted). Active LOW 3-state Output Enable input.
2603 tbl 06
ON OE
FUNCTION TABLE(1)
Inputs Function Hi-Z Load Register FCT534 Outputs Internal DN X X L H L H FCT374/574 Outputs Internal ON Z Z L H Z Z
OE
H H L L H H
CP
ON
Z Z H L Z Z
QN NC NC L H L H
QN
NC NC H L H L
2603 tbl 05
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
u u u u
L H
u
Military 0.5 to +7.0 Unit V
Z = High Impedance NC = No Change = LOW-to-HIGH transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage 0.5 to +7.0 with Respect to GND (3) Terminal Voltage VTERM 0.5 to VCC with Respect to GND TA Operating 0 to +70 Temperature TBIAS Temperature 55 to +125 Under Bias TSTG Storage 55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current 120
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit
pF pF
0.5 to VCC
V °C °C °C W mA
55 to +125 65 to +135 65 to +150 0.5 120
NOTE: 2603 tbl 02 1. This parameter is measured at characterization but not tested.
NOTES: 2603 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
7.13
3
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