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Details, datasheet, quote on part number: IDT5T9310
 
 
Part numberIDT5T9310
Category
Description2.5V LVDS 1:10 Clock Buffer Terabuffer
CompanyIntegrated Device Technology, Inc.
DatasheetDownload IDT5T9310 datasheet
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Specifications, Features, Applications

Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 125ps (max) High speed propagation delay < 1.75ns (max) to 1GHz operation Selectable inputs Hot insertable and over-voltage tolerant inputs / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface Selectable differential inputs to ten LVDS outputs Power-down mode 2.5V VDD Available in VFQFPN package

The IDT5T9310 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9310 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The IDT5T9310 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Symbol VDD VI VO TSTG TJ Input Voltage Output Voltage(2) Storage Temperature Junction Temperature Description Power Supply Voltage Max 0.5 to VDD to +150 Unit V C

Symbol CIN Parameter Input Capacitance Min Typ. Max. 3 Unit pF
NOTE: 1. This parameter is measured at characterization but not tested

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Not to exceed 3.6V.

Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Min. 40 2.3 Typ. +25 2.5 Max. +85 2.7 Unit C V

Symbol A[1:2] I/O I Type Adjustable(1,4) Description Clock input. A[1:2] is the "true" side of the differential clock input. Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for A[1:2]: 3.3V LVTTL VREF 1650mV 2.5V LVTTL VREF = 1250mV Gate control for differential outputs Q1 and Q1 through Q5 and Q5. When G1 is LOW, the differential outputs are active. When G1 is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Gate control for differential outputs Q6 and Q6 through Q10 and Q10. When G2 is LOW, the differential outputs are active. When G2 is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs Complementary clock outputs Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3) Power supply for the device core and inputs Power supply return for all power No connect; recommended to connect to GND

NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes powerup after asserting PD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.




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