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Part: IDT7006L70PF
Category:
Description: High-speed 16k X 8 Dual-port Static RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT7006L70PF datasheet File size : 239 kB
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Datasheet text preview:
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
Integrated Device Technology, Inc.
IDT7006S/L
FEATURES:
· True Dual-Ported memory cells which allow simultaneous access of the same memory location · High-speed access -- Military: 20/25/35/55/70ns (max.) -- Commercial: 15/17/20/25/35/55ns (max.) · Low-power operation -- IDT7006S Active: 750mW (typ.) Standby: 5mW (typ.) -- IDT7006L Active: 750mW (typ.) Standby: 1mW (typ.) · IDT7006 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device · M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave · Busy and Interrupt Flags
· On-chip port arbitration logic · Full on-chip hardware support of semaphore signaling between ports · Fully asynchronous operation from either port · Devices are capable of withstanding greater than 2001V electrostatic discharge · Battery backup operation--2V data retention · TTL-compatible, single 5V (±10%) power supply · Available in a 68-pin PGA, a 68-pin quad flatpack, a 68pin PLCC, and a 64-pin TQFP · Industrial temperature range (40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The IDT7006 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
FUNCTIONAL BLOCK DIAGRAM
OEL
R/
OER
R/
CEL
WL
CER
WR
I/O0L- I/O7L I/O Control I/O Control
I/O0R-I/O7R
BUSYL
(1,2)
BUSYR
Address Decoder
14
(1,2)
A13L A0L
MEMORY ARRAY
Address Decoder
A13R A0R
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.
14
OEL
R/
CEL
WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER
R/
OER
WR
SEMR
(2)
SEML
INTL
(2)
M/S
INTR
2739 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2739/5
6.07
1
IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery. The IDT7006 is packaged in a ceramic 68-pin PGA, a 68pin quad flatpack, a 68-pin PLCC, and a 64-pin TQFP (thin plastic quad flatpack) . Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
I/O1L I/O0L N/C
SEML
4
WL
R/
5
INDEX I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9
8
7
6
3
N/C A13L VCC A12L A11L A10L A9L A8L A7L A6L
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
OEL
CEL
IDT7006 J68-1 F68-1 PLCC / FLATPACK TOP VIEW(3)
A5L A4L A3L A2L A1L A0L
INTL
BUSYL
GND M/S
INTR
BUSYR
A0R A1R A2R A3R A4R
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O7R N/C
N/C A13R GND A12R A11R A10R A9R A8R A7R A6R A5R
WR
OER
SEMR
R/
CER
2739 drw 02
R/ L
SEML
I/O1L I/O0L
INDEX
61 60 64 58 57 56 55 63 62 53 52 59 54 51 50
C EL
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
49
VCC A12L A11L A10L A9L A8L A7L A6L A5L
A13L
O EL
W
48 47 46 45 44
A4L A3L A2L A1L A0L
INTL
IDT7006 PN-64 TQFP TOP VIEW(3)
43 42 41 40 39 38 37 36 35 34
BUSYL
GND M/S
BUSYR
INTR
A0R A1R A2R A3R A4R
17 18 19
26 27 28
20 21 22
29 30 31
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the the actual part-marking.
I/O6R
I/O7R
SEMR
A12R
23 24 25
R/ R
A11R
A10R
32
16
33
C ER
A7R
O ER
A 8R
6.07
A13R
GND
A9R
A6R
A 5R
W
2739 drw 03
2
IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)(1,2)
51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L
50 A4L 49 A3L
48 A2L 47 A1L
46 44 42 A0L BUSYL M/S 45
INTL
40
INTR
38 A1R
36 A3R 35 A4R 32 A7R 30 A9R 34 A5R 33 A6R 31 A8R
10
43 41 39 37 GND BUSYR A0R A2R
09
08
56 57 A11L A10L 58 59 VCC A12L 60 61 N/C A13L 63
07
IDT7006 G68-1 68-PIN PGA TOP VIEW(3)
29 28 A11R A10R 27 26 GND A12R 24 N/C 25 A13R 23
06
05
S E ML C E L OEL R/WL
64
62
65 04
SEMR
20
22
C ER
03
67 66 I/O0L N/C 1 3 68 I/O1L I/O2L I/O4L 2 4 I/O3L I/O5L B C 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 6 8 10 12 14 16 I/O6L VCC I/O0R I/O2R I/O3R I/O5R D E F G H J
OER
21 R/ R
W
02
18 19 I/O7R N/C 17 I/O6R K L
2739 drw 04
01 A INDEX
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port R/WL Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground
2739 tbl 01
CEL
OEL
CER R/WR OER
A0R A13R I/O0R I/O7R
A0L A13L I/O0L I/O7L
SEML INTL BUSYL
M/S VCC
SEMR INTR BUSYR
GND
6.07
3
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