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Part: IDT707288L
Category:
Memory
-> SRAM
Description: High-speed 64k X 16 Bank-switchable Dual-ported SRAM With External Bank Selects
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT707288L datasheet File size : 239 kB
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Datasheet text preview:
Integrated Device Technology, Inc.
HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
DESCRIPTION:
ADVANCED IDT707288S/L
FEATURES:
· 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks - 1 Megabit of memory on chip · Fast asynchronous address-to-data access time: 20ns · User-controlled input pins included for bank selects · Independent port controls with asynchronous address & data busses · Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option · Interrupt flags with programmable masking · Dual Chip Enables allow for depth expansion without external logic · UB and LB are available for bus matching to x8 or x16 busses; also support very fast banking · TTL-compatible, single 5V (±10%) power supply · Available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA)
The IDT707288 is a high-speed 64K x 16 (1M bit) BankSwitchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate controls, addresses, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow inter-processor communications. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288 offers a maximum address-to-data access time as fast as 20ns, while typically operating on only 900mW of power, and is available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
R/
FUNCTIONAL BLOCK DIAGRAM
R/
L 0L CE1L L L L
MUX
R
CONTROL LOGIC
16Kx16 MEMORY ARRAY (BANK 0) MUX
CONTROL LOGIC
0R CE1R R R R
I/O8L-15L I/O0L-7L
I/O CONTROL
MUX 16Kx16 MEMORY ARRAY (BANK 1) MUX
I/O CONTROL
I/O8R-15R I/O0R-7R
A13L A0L(1)
ADDRESS DECODE
ADDRESS DECODE
A13R A0R(1)
BA1L BA0L
BANK DECODE MUX 16Kx16 MEMORY ARRAY (BANK 3) MUX
BANK DECODE
BA1R BA0R
BKSEL3(2) BKSEL0(2)
BANK SELECT A5L(1) A0L(1) L/ L
L
MAILBOX INTERRUPT LOGIC
A5R(1) A0R(1) R/
R
R
R/
L L
L L
R/
R
R R R
3592 drw 01
NOTES: 1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3592/-
6.29
1
IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
FUNCTIONALITY:
The IDT707288 is a high-speed asynchronous 64K x 16 Bank-Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled Bank Select input pins , and each of these pins is associated with a specific bank within the memory array. Access to a specific bank is gained by placing the associated Bank Select pin in the appropriate state: VIH assigns the bank to the left port, and VIL assigns the bank to the right port (See Truth Table I). Once a bank is assigned to a particular port, the port has full access to read and write within that bank. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The IDT707288 provides mailboxes to allow inter-processor communications. Each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. These mailboxes are external to the common SRAM array, and are accessed by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. The interrupted port can clear the interrupt by reading the upper byte. This read will not alter the contents of the mailbox. If desired, any source of interrupt can be independently masked via software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. The information
in this register provides post-mask signals: Interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. Truth Table II gives a detailed explanation of the use of these registers.
PIN NAMES
A0 - A13 (1,6) BA0 - BA1
MBSEL (1)
(1)
Address Inputs Bank Address Inputs Mailbox Access Control Gate Bank Select Inputs Read/Write Enable Output Enable Chip Enables I/O Byte Enables Bidirectional Data Input/Output Interrupt Flag (Output)(3) +5V Power Ground
BKSEL R/W (1)
OE
(1)
(2)
CE0 UB
, CE1 (1) , LB (1)
I/O0 I/O15 (1)
INT (1)
VCC GND (5)
(4)
3592 tbl 01 NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details. 3. Generated upon mailbox access. 4. All Vcc pins must be connected to power supply. 5. All GND pins must be connected to ground supply. 6. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as bank address or memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs.
PIN CONFIGURATIONS (1,2)
GND GND
I NT R I NT L
INDEX
A6L A7L A8L A9L A10L A11L A13L NC BKSEL0
L BL U BL C E0 L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A5L A4L A3L A2L A1L A0L BA1L BA0L A12L NC BKSEL1
BKSEL2 A12R BA0R BA1R A0R A1R A2R A3R A4R A5R
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
A6R A7R A8R A9R A10R A11R A13R NC BKSEL3
L BR U BR C E0 R
IDT707288 PN100-1 100-PIN TQFP TOP VIEW(3)
CE1L
MBS EL L
CE1R
MBS EL R
Vcc R/WL
OE L
GND R/WR
O ER
GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
3592 drw 02
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.29 2
I/O9L I/O8L Vcc I/O7 L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC
IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CON'T.) (1,2)
81 80 77 74 72
UBR
69
MB SEL R
68
65
63
60
57
54
12
A7R
84
A8R
83
A11R
78
BK SEL 3
76
GND GND
67 64
NC
61
I/O13R I/O10R
59 56
NC
53
73
LBR
70
11
A4R
87
A5R
86
A10R
82
A13R
79
CE 1R R/WR
71
CE0R
GND I/O14R I/O12R I/O9R
62 58 55 51
NC
50
75
66
OER
10
A1R
90
A2R
88
A6R
85
A9R
NC
I/O15R I/O11R
NC
52
I/O8R
49
I/O7R
47
09
BA0R
92
A0R
91
A3R
89
NC
48
Vcc
46
I/O5R
45
08
BK SEL2
95
A12R
94
BA1R
93
INT R
I/O6R
44
I/O4R
43
I/O3R
42
07
GND
96
GND
97
IDT707288 G108-1
I/O2R
39
I/O1R
40
I/O0R
41
98
06
INT L
BK SEL 1
100
NC
102
I/O1L
108-Pin PGA Top View
(3)
I/O0L
37
GND
38
99
35
05
A12L
101
BA0L
103
A0L
106 A4L 1 4 8 12 17 21 25
I/O4L
31
I/O2L
34
GND
36
04
BA1L
104
A1L
105
Vcc
28
I/O5L
32
I/O3L
33
03
A2L
107 2
A3L
5
A7L
7
A10L
BK SEL0
10
UB L
CE 1L
13
MB SELL
GND
16
OE L
I/O14L I/O10L
19 22
NC
24
I/O7L
29
I/O6L
30
02
A5L
108
A8L
3 6
A11L
9
NC
GND I/O13L
18 20
I/O11L
23 26
NC
I/O8L
27
11
LB L CE0L
14
15
01
A6L A
A9L B
A13L C
Vcc F
R/W L G
NC H
I/O15L J
I/O12L K
I/O9L L
NC M
3592 drw 03
D
E
I NDEX
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking.
6.29
3
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