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Part: IDT707L25JI
Category:
Interface and Interconnect
-> Multi-Ports
Description: 32K X 8 Dual-port RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT707L25JI datasheet File size : 239 kB
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Datasheet text preview:
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
Features
x x
IDT7007S/L
x
x
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Military: 25/35/55ns (max.) Industrial: 55ns (max.) Commercial: 15/20/25/35/55ns (max.) Low-power operation IDT7007S Active: 850mW (typ.) Standby: 5mW (typ.) IDT7007L Active: 850mW (typ.) Standby: 1mW (typ.) IDT7007 easily expands data bus width to 16 bits or more
x
x x x
x x x x
using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 68-pin PGA and PLCC and a 80-pin TQFP Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL A14L A0L
(1,2)
I/O0R-I/O7R I/O Control BUSYR A14R A0R
(1,2)
Address Decoder
15
MEMORY ARRAY
15
Address Decoder
CEL OEL R/WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER OER R/WR
SEML (2) INTL
NOTES: 1 . (MASTER): BUSY is output; (SLAVE): BUSY is input. 2 . BUSY and INT outputs are non-tri-stated push-pull.
M/S
SEMR INTR(2)
2940 drw 01
JUNE 1999
1
DSC 2940/8
IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter a very LOW standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 850mW of power. The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, and an 80-pin thin quad flatpack, TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
I/O1L I/O0L N/C
OEL R/WL SEML CEL
6 5 4 3
INDEX I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9
8
7
A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
IDT7007J J68-1(4) 68-Pin PLCC Top View(5)
A5L A4L A3L A2L A1L A0L
INTL BUSYL
GND M/S
BUSYR INTR
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A0R A1R A2R A3R A4R
2940 drw 02
OER R/WR SEMR CER
I/O7R N/C
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . Package body is approximately .95 in x .95 in x .17 in. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part marking.
A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R
2
IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
I/O1L I/O0L N/C OEL R/WL SEML CEL N/C A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L N/C N/C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INDEX N/C I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC N/C GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C
7007PF PN80-1(4) 80-Pin TQFP Top View(5)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR , INTR A0R A1R A2R A3R A4R N/C N/C
2 940 drw 03
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . Package body is approximately 14mm x 14mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part marking.
I/O7R N/C OER R/WR SEMR CER N/C A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R N/C N/C
3
IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L 50 A4L 49 A3L 48 A2L 47 A1L 46 44 42 A0L BUSYL M/S 40 38 INTR A1R 36 A3R 35 A4R 32 A7R 30 A9R 28 A11R 26 GND 34 A5R 33 A6R 31 A8R 29 A10R 27 A12R
10
45 43 41 39 37 INTL GND BUSYR A0R A2R
09
08
57 56 A11L A10L 59 58 VCC A12L 61 60 A13L
07
IDT7007G G68-1(4) 68-Pin PGA Top View(5)
06
A14L
63 62 05 SEML CEL 04 65 64 OEL R/WL 67 66 I/O0L N/C 1 3 68 I/O1L I/O2L I/O4L 2 01 A INDEX
NOTES: 1 . All Vcc pins must be connected to power supply 2 . All GND pins must be connected to power supply 3 . Package body is approximately 1.8 in x 1.8 in x .16 in. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part marking.
24 25 A14R A13R 22 23 SEMR CER 20 OER 21 R/WR
03
02
5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 6 I/O6L D 8 10 12 14 16 VCC I/O0R I/O2R I/O3R I/O5R E F G H J
18 19 I/O7R N/C 17 I/O6R
K
4 I/O3L I/O5L B C
L
2940 drw 04
Pin Names
Left Port C EL R/WL OEL A0 L - A14L I/ O0 L - I/O7L SEML INTL BUSYL C ER R/WR OER A0R - A14R I/ O0R - I/O7R SEMR INTR BUSYR M/ S VCC GND Right Port Names Chip Enables Re ad / Write Enable Outp ut Enable Ad d re s s Data Input/Output Se map ho re Enable Inte rrup t Flag Bus y Flag Mas te r or Slave Select Po we r Gro und
2940 tbl 01
4
IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs CE H L L X R/W X L H X OE X X L H SEM H H H X Outputs I/O0-7 High-Z DATAIN DATAOUT High-Z De sele cte d: Power-Down Write to Memory Re ad Memory Outp uts Disabled
2940 tbl 02
Mode
NOTE: 1 . A0L A14L A0R A14R
Truth Table II: Semaphore Read/Write Control(1)
Inputs CE H H L R/W H OE L X X S EM L L L Outputs I/O0 -7 DATA OUT DATA IN
______
Mode Re ad Semap ho re Flag Data Out (I/O0-I/O7) Write I/O0 into Semaphore Flag No t Allowed
2940 tbl 03
X
NOTE: 1 . There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Te rminal Voltage with Respect to GND Te mp e rature Und e r Bias Sto rag e Te mp e rature DC Output Curre nt Commercial & Industrial -0. 5 to +7.0 Military -0. 5 to +7.0 Unit V
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Military Ambient Temperature -55OC to+125OC 0OC to +70OC -40 C to +85 C
O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2940 tbl 05
TBIAS TSTG IOUT
-55 to +125 -55 to +120 50
-55 to +135 -65 to +150 50
o
C C
Co mme rcial Ind ustrial
o
mA
2940 tbl 04
NOTES: 1 . This is the parameter TA. 2 . Industrial temperature: for other speeds, packages and powers contact your sales office.
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to Vcc + 10%.
Recommended Operating Conditions
Symbol VCC GND Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Min. 4.5 0 2.2 -0. 5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 6.0(2) 0.8
Unit V V V V
2940 tbl 06
Capacitance (TA = +25°C, f = 1.0mhz)
Symbol CIN COUT Parameter
(1)
VIH Unit pF pF
2940 tbl 07
Conditions
(2)
Max. 9 10
V IL
Inp ut Capacitance Outp ut Capacitance
VIN = 3dV VOUT = 3dV
NOTES: 1 . VIL > -1.5V for pulse width less than 10ns. 2 . VTERM must not exceed Vcc + 10%.
NOTES: 1 . This parameter is determined by device characterization but is not production tested. TQFP package only. 2 . 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
5
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