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Part: IDT70824
Category:
Memory
-> Multiport->64K
Description: Sequential Access Port 1 RAM Port 2: 4kx16
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT70824 datasheet File size : 239 kB
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Datasheet text preview:
HIGH SPEED 64K (4K X 16 BIT) IDT70824S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAMTM)
Features
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High-speed access Military: 35/45ns (max.) Commercial: 20/25/35/45ns (max.) Low-power operation IDT70824S Active: 775mW (typ.) Standby: 5mW (typ.) IDT70824L Active: 775mW (typ.) Standby: 1mW (typ.) 4K x 16 Sequential Access Random Access Memory (SARAMTM) Sequential Access from one port and standard Random Access from the other port Separate upper-byte and lower-byte control of the Random Access Port High speed operation 20ns tAA for random access port 20ns tCD for sequential port 25ns clock cycle time Architecture based on Dual-Port RAM cells
x x x x x
Compatible with Intel BMIC and 82430 PCI Set Width and Depth Expandable Sequential side Address based flags for buffer control Pointer logic supports up to two internal buffers Battery backup operation - 2V data retention TTL-compatible, single 5V (+10%) power supply Available in 80-pin TQFP and 84-pin PGA Military product compliant to MIL-PRF-38535 QML Industrial temperature range (40°C to +85°C) is available for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
A0-11 CE OE R/W LB LSB MSB UB CMD I/O0-15
12
Random Access Port Controls
Sequential Access Port Controls
4K X 16 Memory Array
16 12 12 12 12 12
RST SCLK CNTEN SOE SSTRT1 SSTRT2 SCE SR/W SLD SI/O0-15 ,
Dat aL AddrL
DataR AddrR
16
Reg. 12
16
RST
Pointer/ Counter
Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status
12
EOB1 COMPARATOR EOB2
3099 drw 01
APRIL 2000
1
©2000 Integrated Device Technology, Inc. DSC-3099/5
6.07
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
quencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 775mW of power at maximum highspeed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
The IDT70824 is packaged in a 80-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
INDEX SI/O1 SI/O0 GND N/C SCE SR/W RST SLD SSTRT2 SSTRT1 GND GND CNTEN SOE SCLK GND EOB2 EOB1 VCC I/O0
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 2 58 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 56 55 54 53
SI/O2 SI/O3 VCC SI/O4 SI/O5 SI/O6 SI/O7 GND SI/O8 SI/O9 SI/O10 SI/O11 VCC SI/O12 SI/O13 SI/O14 SI/O15 GND N/C GND
IDT70824PF PN80-1(4) 80-Pin TQFP Top View(5)
52 51 50 49 48 47 46 45 44 43 42 41 20 21 2 2 2 3 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Configurations(1,2,3)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC VCC A1 A0 CMD CE LB UB R/W OE
3099 drw 02 ,
63
61
I/O1 GND I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 VCC I/O12 I/O13 I/O14 I/O15 GND
60 58 55 54 51 SSTRT2 50 48 46 45 42
I/O1
66
VCC
64
EOB1
62
GND CNTEN GND
59 56 49
SR/W NC
47 44
GND
43
NC
40
11 10 09 08 07 06 05 04 03 02 01
,
I/O2
67
NC
65
I/O0 EOB2 SOE RST SLD
57 53 52 SSTRT1
SCE SI/O0 SI/O1 SI/O3
41 39
I/O3 GND
69 68
SCLK GND
SI/O2 VCC
38 37
I/O4
72
VCC
71 73 33
SI/O4 SI/O5
35 34
I/O7
75
I/O6 GND
70 74
IDT70824G G84-3(4) 84-Pin PGA Top View(5)
SI/O8 SI/O7 GND
32 31 36
I/O9
76
I/O5
77
I/O8
78
SI/O9 SI/O10 SI/O6
28 29 30
I/O10 I/O11 VCC
79 80
SI/O12 VCC SI/O11
26 27
I/O12 I/O13
81 83 7 11 12
SI/O14 SI/O13
23 25
I/O14
82 1
NC
2 5
CMD VCC
8 10
A2
14 17 20
NC SI/O15
22 24
I/O15 GND
84 3 4
OE
6
LB
9
A0 A1 E
VCC
15
A4
13
A7
16
A10
18
GND GND
19 21
NC A Pin 1 Designator
R/W B
UB C
CE D
A5 F
A3 G
A6 H
A8 J
A9 K
A11 L
3099 drw 03
NOTES: 1 . All VCC pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . PN80-1 package body is approximately 14mm x 14mm x 1.4mm. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
2
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Pin Descriptions: Random Access Port(1)
SYMBOL A0-A11 I/O0-I/O1 5 CE NAME Ad d re ss Lines Inp uts/Outp uts Chip Enable I/O I I I DESCRIPTION Ad d re ss inputs to access the 4096-word (16-Bit) memory array. Rand o m access data inputs/outputs for 16-Bit wide data. When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time. When CMD is LOW, address lines A0-A2, R/W, and inputs and outputs I/O0-I/O12, are used to access the co ntro l register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the same time. If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. When LB is LOW, I/O0-I/O7 are accessible for re ad and write operations. When LB is HIGH, I/O0-I/O7 are tristate d and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and is asynchronous fro m LB. Se ve n +5 power supply pins. All VCC pins must be connected to the same +5V VCC supply. Te n ground pins. All ground pins must be connected to the same ground supply.
3099 tbl 01
CMD
Co ntro l Register Enable
I
R/W
Re ad /Write Enable
I
OE L B, UB
Outp ut Enable Lo we r Byte, Upper Byte Enab les
I I
VCC GND
Po we r Supply Gro und
I I
Pin Descriptions: Sequential Access Port(1)
SYMBOL SI/O0-15 SCLK SC E NAME Inp uts/Outp uts Clo ck Chip Enable I/O I/O I I DESCRIPTION Se q ue ntial data inputs/outputs for 16-bit wide data. SI/O0-SI/O1 5,SC E, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments by 1 on each LOW-TO-HIGH transition of SCLK when CNTEN is LOW. When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transitio n of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random acce ss port. When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is ind e pe nd e nt of CE. Whe n SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination o f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the datain register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. EOB1 or EOB2 is output low when the address pointer is incremented to match the address stored in the end o f buffer registers. The flags can be cleared by either asserting RST LOW or by writing ze ro into Bit 0 and/or Bit 1 of the control registe r at address 101. EOB1 and EOB2 are dependent on separate internal registers, and the re fore separate match addresses. SOE controls the data outputs and is independe nt of SCLK. When SOE is LOW, output buffers and the se q uentially ad d resse d data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state. SOE is asynchronous to SCLK. When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
3099 tbl 02
CN TEN SR/W
Co unte r Enable Re ad /Write Enable
I I
SLD
Ad d re ss Pointer Load Control
I
SSTRT1, SSTRT2 EOB1, EOB2
Lo ad Start of Address Re g iste r End of Buffer Flag
I
O
SOE
Outp ut Enable
I
RST
Re se t
I
NOTE : 1 . "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.42 3
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