|
|
Part: IDT70824L
Category:
Memory
Description: High-speed 4k X 16 Sequential Access Random Access Memory ( Saram )
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT70824L datasheet File size : 239 kB
Request For quote: Find where to buy IDT70824L
Datasheet text preview:
HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAMTM)
Integrated Device Technology, Inc.
IDT70824S/L
FEATURES:
· 4K x 16 Sequential Access Random Access Memory (SARAMTM) - Sequential Access from one port and standard Random Access from the other port - Separate upper-byte and lower-byte control of the Random Access Port · High speed operation - 20ns tAA for random access port - 20ns tCD for sequential port - 25ns clock cycle time · Architecture based on Dual-Port RAM cells · Electrostatic discharge > 2001V, Class II · Compatible with Intel BMIC and 82430 PCI Set · Width and Depth Expandable · Sequential side - Address based flags for buffer control - Pointer logic supports up to two internal buffers · Battery backup operation - 2V data retention · TTL-compatible, single 5V (+10%) power supply · Available in 80-pin TQFP and 84-pin PGA · Military product compliant to MIL-STD-883. · Industrial temperature range (40°C to +85°C) is available, tested to military electrical specifications.
DESCRIPTION:
The IDT70824 is a high-speed 4K x 16-bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter sequencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 900mW of power at maximum high-speed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70824 is packaged in a 80-pin Thin Plastic Quad Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0-11
12
RST
SCLK Random Access Port Controls Sequential Access Port Controls
CE OE R/W LB LSB UB MSB CMD
I/O0-15
4K X 16 Memory Array
16 12
CNTEN SOE SSTRT1 SSTRT2 SCE SR/W SLD
SI/O0-15
DataL AddrL
12
DataR AddrR
16
Reg. 12
16
RST
12
12 12
Pointer/ Counter
Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status
12
EOB1
COMPARATOR
EOB2
3099 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3099/3
6.30
1
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (1,2)
INDEX SI/O1 SI/O0 GND N/C
SI/O2 SI/O3 V CC SI/O4 SI/O5 SI/O6 SI/O7 GN D SI/O8 SI/O9 SI/O10 SI/O11 VCC SI/O12 SI/O13 SI/O14 SI/O15 GN D N/C GN D
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 2 58 3 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 56 55 54 53
SCE
RST
SR/
W
SSTRT2 SSTRT1
SLD
IDT70824 PN80-1 TQFP TOP VIEW(3)
52 51 50 49 48 47 46 45 44 43 42
CNTEN
GND GND
SOE
SCLK GND
EOB2 EOB1
VCC I/O0
CMD CE
LB UB
R/
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC VCC A1 A0
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
OE
W
I/O1 GND I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 VCC I/O12 I/O13 I/O14 I/O15 GND
63 61 60 58 55 54 48 46
3099 drw 02
I/O1
66
VCC
64
EOB1
62
51
45
42
GND CNTEN GND SSTRT2 SR/W NC
59 56
GND
43
NC
40
11 10 09 08 07 06 05 04 03 02 01
I/O2
67
NC
65
I/O0 EOB2
SOE
49
RST SLD SCE
52
50
47
44
SI/O0 SI/O1 SI/O3
41 39
57
53
I/O3 GND
69 68
SCLK GND SSTRT1
SI/O2 VCC
38 37
I/O4
72
VCC
71 73 33
SI/O4 SI/O5
35 34
I/O7
75
I/O6 GND
70 74
IDT70824 G84-3 84-PIN PGA TOP VIEW (3)
SI/O8 SI/O7 GND
32 31 36
I/O9
76
I/O5
77
I/O8
78
SI/O9 SI/O10 SI/O6
28 29 30
I/O10 I/O11 VCC
79 80
SI/O12 VCC SI/O11
26 27
I/O12 I/O13
81 83 7
SI/O14 SI/O13
I/O14
82 1
NC
2
CMD
A0
11
12
23
25
VCC
10
A2
14 17 20
NC SI/O15
22 24
I/O15 GND
84 3
OE
5
LB
8
VCC
15
A4
13
A7
16
A10
18
GND GND
19 21
NC A INDEX
R/
W
4
UB
C
6
CE
D
9
A1 E
A5 F
A3 G
A6 H
A8 J
A9 K
A11 L
B
3099 drw 03
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.30 2
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL A0-A11
CE
NAME Address Lines Chip Enable
I/O(1) I I I
DESCRIPTION Address inputs to access the 4096-word (16 bit) memory array. Random access data inputs/outputs for 16-bit wide data. When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMD may not be LOW at the same time. When CMD is LOW, Address lines A0-A2, R/W, and inputs/outputs I/O0-I/O11, are used to access the control register, the flag register, and the start and end of buffer registers. CMD and CE may not be LOW at the same time. If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the high-impedance state. When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0I/O7 are tri-stated and blocked during read and write operations. UB controls access for I/O8I/O15 in the same manner and is asynchronous from LB. Seven +5V power supply pins. All Vcc pins must be connected to the same +5V VCC supply. Ten Ground pins. All Ground pins must be connected to the same Ground supply.
3099 tbl 01
I/O0-I/O15 Inputs/Outputs
CMD
Control Register Enable Read/Write Enable
I
R/W
I
OE
Output Enable Lower Byte, Upper Byte Enables Power Supply Ground
I I
LB UB
,
VCC GND
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL NAME SI/O0-15 Inputs SCLK Clock I/O(1) DESCRIPTION I/O Sequential data inputs/outputs for 16-bit wide data. I SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH transition of SCLK when CNTEN is LOW. Chip Enable I When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All data is retained, unless altered by the random access port. Counter Enable I When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is independant of SCE. Read/Write Enable I When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High transistion of SCLK if SR/W or SCE is High. Address Pointer I When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer Load Control changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. Load Start of I When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the Address Register address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. End of Buffer Flag O EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are dependent on separate internal registers, and therefore separate match addresses. Output Enable I SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers and the sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in the high-impedance state. SOE is asynchronous to SCLK. Reset I When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
3099 tbl 02
SCE
CNTEN
SR/W
SLD
SSTRT SSTRT
1, 2
EOB EOB
1, 2
SOE
RST
NOTE: 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.30
3
Others parts begin by id
ID-1 ID-2 ID-3 ID-4 ID-5 ID-6 ID-7 ID-8 ID-9 ID-10 ID-11 ID-12 ID-13 ID-14 ID-15 ID-16 ID-17 ID-18 ID-19 ID-20 ID-21 ID-22 ID-23 ID-24 ID-25 ID-26 ID-27 ID-28 ID-29 ID-30 ID-31 ID-32 ID-33 ID-34 ID-35 ID-36 ID-37 ID-38 ID-39 ID-40 ID-41 ID-42 ID-43 ID-44 ID-45 ID-46 ID-47 ID-48 ID-49 ID-50 ID-51 ID-52 ID-53 ID-54 ID-55 ID-56 ID-57 ID-58 ID-59 ID-60 ID-61 ID-62 ID-63 ID-64 ID-65 ID-66 ID-67 ID-68 ID-69 ID-70 ID-71 ID-72 ID-73 ID-74 ID-75 ID-76 ID-77 ID-78 ID-79 ID-80 ID-81 ID-82 ID-83 ID-84 ID-85 ID-86 ID-87 ID-88 ID-89 ID-90 ID-91 ID-92 ID-93 ID-94 ID-95 ID-96 ID-97 ID-98 ID-99 ID-100 ID-101 ID-102 ID-103 ID-104 ID-105 ID-106 ID-107 ID-108 ID-109 ID-110 ID-111 ID-112 ID-113 ID-114 ID-115 ID-116 ID-117 ID-118 ID-119 ID-120 ID-121 ID-122 ID-123 ID-124 ID-125 ID-126 ID-127 ID-128 ID-129 ID-130 ID-131 ID-132 ID-133 ID-134 ID-135 ID-136 ID-137 ID-138 ID-139 ID-140 ID-141 ID-142
|
|
|
