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Part: IDT70T633S15DD
Category:
Communication
-> Telephony
-> Line Interface
Description: High-speed 2.5v 512/256k X 18 Asynchronous Dual-port Static RAM With 3.3v 0r 2.5v Interface
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT70T633S15DD datasheet File size : 398 kB
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Datasheet text preview:
Features
HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY IDT70T633/1S
True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access Commercial: 8/10/12/15ns (max.) Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags
Full hardware support of semaphore signaling between ports on-chip On-chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array Industrial temperature range (40°C to +85°C) is available for selected speeds
UBR LB R
Functional Block Diagram
U BL L BL
R/W L
B E 0 L B E 1 L B E 1 R B E 0 R
R /WR
CE0 L
CE1 L
CE0 R CE1 R
OEL Dout0-8 _L Dout9-17_L Do ut0-8_R Dout9-17_R
OER
51 2/2 56 K x 1 8 M EM O R Y A R RA Y
I/O0 L - I /O1 7L Din _L Din_R I/O0 R - I/ O1 7R
A18L( 1) A 0L
A dd r es s D ec od e r
ADDR_L
ADDR_R
Ad dre ss D e co de r
A1 8R (1) A0 R
TDI
OEL
CE0 L CE1 L
R/ WL
ARBI TRATION INTERRUPT SEMAPHORE LOGI C
OER
C E0R CE1R
TDO
JT AG
TCK T MS T R ST
R/WR
B USYL(2,3) SEM L I NTL(3)
( 4)
BU SYR(2,3)
M/ S
SEM R IN TR(3)
NOTES: 1 . Address A18x is a NC for IDT70T631. 2 . BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 3 BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4 . The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZL
ZZ C ON TR OL LO GI C
ZZR
(4 )
56 70 dr w 01
NOVEMBER 2003
DSC-5670/3
1
©2003 Integrated Device Technology, Inc.
IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down
Description
feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T651/9 has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performance levels. The 70T633/1 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 2.5V.
2
IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3)
70T633/1BC BC-256 (5,6) 256-Pin BGA Top View
A2 A3 A4 A5 A6 A7 A8 A9 A 10 A11 A 12 A13 A 14 A15 A 16
03 /13 /03
A1
NC
B1
TDI
B2
NC
B3
A17L
B4
A 14L
B5
A11L
B6
A8L
B7
NC
B8
CE1L
B9
OEL
B10
INT L
B11
A5L
B 12
A2L
B13
A0L
B 14
NC
B15
NC
B 16
NC
C1
NC
C2
TDO A18L(4) A15L
C3 C4 C5
A12L
C6
A9L
C7
UBL
C8
CE0L R/WL
C9 C10
NC
C11
A4L
C12
A1L
C13
NC
C14
NC
C15
NC
C16
NC
D1
I/O9L
D2
VSS
D3
A16L
D4
A13L
D5
A10L
D6
A7L
D7
NC
D8
L BL
D9
SEML BU SYL
D10 D11
A6L
D12
A3L
D13
OPTL
D14
NC
D15
I /O8L
D16
NC
E1
I/O9R
E2
NC
E3
VDD VDDQL VDDQ L VDDQR VDDQ R VDDQL VDDQ L VDDQR VDDQR VDD
E4 E5 E6 E7 E8 E9 E 10 E11 E12 E13
NC
E 14
NC
E15
I /O8R
E 16
I/O10R I/O 10L
F1 F2
NC
F3
VDDQL VDD
F4 F5
VDD
F6
VSS
F7
VSS
F8
VSS
F9
VSS
F10
VDD
F1 1
VDD VDDQR
F12 F13
NC
F14
I/O7L I /O7R
F15 F16
I/O11L
G1
NC
G2
I/ O11R VDDQL VDD
G3 G4 G5
NC
G6
VSS
G7
VSS
G8
VSS
G9
VSS
G 10
VSS
G1 1
VDD VDDQR I /O6R
G12 G13 G14
NC
G15
I/O6L
G16
NC
H1
NC
H2
I/ O12L VDDQR VSS
H3 H4 H5
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VDDQL I/O5L
H13 H14
NC
H15
NC
H16
NC
J1
I/O12R
J2 J3
NC VDDQ R VSS
J4 J5
VSS
J6
VSS
J7
VSS
J8
VSS
J9
VSS
J 10
VSS
J 11
VSS
J12
VDDQL
J13
NC
J14
NC
J15
I/O5R
J 16
I/O13L I/O 14R I/O13R VDDQL ZZ R
K1 K2 K3 K4 K5
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
K 10
VSS
K11
ZZL VDDQR I /O4R I/O3R I/O 4L
K12 K13 K14 K15 K16
NC
L1
NC
L2
I/ O14L VDDQL VSS
L3 L4 L5
VSS
L6
VSS
L7
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VDDQR NC
L13 L14
NC
L15
I/O3L
L16
I/O15L
M1
NC
M2
I/ O15R VDDQR VDD
M3 M4 M5
NC
M6
VSS
M7
VSS
M8
VSS
M9
VSS
M 10
VSS
M11
VDD
M12
VDDQL I /O2L
M13 M14
NC
M15
I/O2R
M 16
I/O16R I/O 16L
N1 N2
NC
N3
VDDQR
N4
VDD
N5
VDD
N6
VSS
N7
VSS
N8
VSS
N9
VSS
N10
VDD
N11
VDD VDDQL I /O1R I/O1L
N12 N13 N14 N15
NC
N16
NC
P1
I/O17R
P2
NC
P3
VDD VDDQR VDDQR VDDQL VDDQ L VDDQR V DDQR VDDQL VDDQL VDD
P4 P5 P6 P7 P8 P9 P10 P11 P 12 P13
NC
P 14
I/O0R
P15
NC
P 16
NC
R1
I/O 17L T MS
R2 R3
A16R
R4
A13R
R5
A10R
R6
A7R
R7
NC
R8
L BR SEMR BUSYR
R9 R10 R11
A6R
R12
A3R
R13
NC
R14
NC
R15
I/O 0L
R16
NC
T1
NC
T2
TRST A18R(4) A15R
T3 T4 T5
A12R
T6
A9R
T7
UBR
T8
CE0R R/WR
T9 T10
M/ S
T11
A4R
T 12
A1R
T13
OP TR
T1 4
NC
T15
NC
T 16
,
NC
TCK
NC
A17R
A14R
A11R
A8R
NC
CE1R
OER
INT R
A5R
A2R
A0R
NC
NC
5670 drw 02c NOTES: 1 . All VDD pins must be connected to 2.5V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3 . All VSS pins must be connected to ground supply. 4 . A18X is a NC for IDT70T631. 5 . Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6 . This package code is used to reference the package diagram.
,
3
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