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Part: IDT70T651S12BC
Category:
Communication
-> Telephony
-> Line Interface
Description: High-speed 2.5v 256/128k X 36 Asynchronous Dual-port Static RAM With 3.3v 0r 2.5v Interface
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT70T651S12BC datasheet File size : 398 kB
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Datasheet text preview:
Features
HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY IDT70T651/9S
True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access Commercial: 8/10/12/15ns (max.) Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T651/9 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad Flatpack and 208-ball fine pitch Ball Grid Array. Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
BE3L BE2 L BE1L BE0 L BE 3R BE2R BE 1R BE0 R
R /W L
CE0 L C E1L
BB EE 01 LL BB EE 23 LL BBBB EEEE 3210 R RRR
R /WR
CE0R CE1R
OEL
Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R Dout18-26_L Dout18-26_R Dout27-35_L Dout27-35_R
O ER
256/128K x 36 MEM OR Y AR RAY I/O0 L- I/O 35L
Di n_L Di n_R
I/O 0R - I/O 35R
A 17 L(1) A0 L
Addre ss Decoder
ADDR_L
ADDR_R
Address D eco der
A17R(1) A0R
C E0L C E1L O EL R/WL B USYL (2 ,3) SEM L INTL(3)
ZZL
(4 )
ARBITRATION INT ERRUPT SEM APHOR E LO GIC
OE R R /WR
CE0 R CE1 R
TDI TD O
JTA G
TC K TMS T R ST
M/S
BUS YR(2,3 ) SE MR INT R(3)
ZZR
(4 )
LOG IC NOTES: 1 . Address A17x is a NC for IDT70T659. 2 . BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 3 . BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4 . The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZ CO NT RO L
4 869 drw 01
NOVEMBER 2003
DSC-5632/3
1
©2003 Integrated Device Technology, Inc.
IDT70T651/9S High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down
Description
feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T651/9 has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performance levels. The 70T651/9 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.
2
IDT70T651/9S High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3)
70T651/9BC BC-256 (5,6) 256-Pin BGA Top View
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
03/18/03
A1
NC
B1
TD I
B2
NC
B3
A17L( 4) A14L
B4 B5
A11L
B6
A 8L
B7
BE2L
B8
CE1L
B9
OEL
B10
INTL
B11
A5L
B12
A2L
B13
A0L
B14
NC
B15
NC
B16
I/O18L
C1
NC
C2
TDO
C3
NC
C4
A15L
C5
A12L
C6
A 9L
C7
BE3L
C8
CE0L R/WL
C9 C10
NC
C11
A4L
C12
A1L
C13
NC
C14
I/O17L
C15
NC
C16
I/O18R I/O19L VSS
D1 D2 D3
A16L
D4
A13L
D5
A10L
D6
A7L
D7
BE1L BE0L SEML BUSYL A6L
D8 D9 D10 D11 D12
A3L
D13
OPTL I/ O17R I/O16L
D14 D15 D16
I/O20R I/O19R I/ O20L
E1 E2 E3
VDD
E4
VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16
I/O21R I/O21L I /O22L VDDQL VDD
F1 F2 F3 F4 F5
VDD
F6
VSS
F7
VSS
F8
V SS
F9
VSS
F10
VDD
F 11
VDD VDDQR I/ O13L I/O14L I/O14R
F12 F13 F14 F15 F16
I/O23L I/O22R I/ O23R VDDQL VDD
G1 G2 G3 G4 G5
NC
G6
VSS
G7
VSS
G8
V SS
G9
VSS
G10
VSS
G1 1
VDD VDDQR I/O12R I/O13R I/O12L
G1 2 G13 G14 G15 G16
I/O24R I/O24L I/ O25L VDDQR VSS
H1 H2 H3 H4 H5
VSS
H6
VSS
H7
VSS
H8
V SS
H9
VSS
H10
VSS
H11
VSS
H12
VDDQL I/ O10L I/O11L I/O11R
H13 H14 H15 H16
I/ O26L I/O25R I /O26R VDDQ R VSS
J1 J2 J3 J4 J5
VSS
J6
VSS
J7
VSS
J8
VSS
J9
V SS
J 10
VSS
J 11
VSS
J12
VDDQ L I/O9R
J13 J14
IO9L I/O10R
J15 J16
I/O27L I/O28R I /O27R VDDQL ZZR
K1 K2 K3 K4 K5
VSS
K6
VSS
K7
VSS
K8
V SS
K9
VSS
K 10
VSS
K 11
ZZL VDDQR I /O8R I/O7R I/O8L
K12 K13 K14 K15 K16
I/O29R I/ O29L I/ O28L VDDQL VSS
L1 L2 L3 L4 L5
VSS
L6
VSS
L7
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VDDQR I/O6R I /O6L I/O7L
L13 L14 L15 L16
I/O30L I/O31R I/ O30R VDDQR VDD
M1 M2 M3 M4 M5
NC
M6
VSS
M7
VSS
M8
V SS
M9
V SS
M10
VSS
M11
VDD
M12
VDDQL I/O5L
M13 M14
I/ O4R I/O5R
M15 M16
I /O32R I/O32L I/ O31L VDDQR
N1 N2 N3 N4
VDD
N5
VDD
N6
VSS
N7
VSS
N8
VSS
N9
VSS
N10
VDD
N11
VDD VDDQL I/O3R I /O3L I/O4L
N12 N13 N14 N15 N16
I/O33L I/O34R I/O33R VDD VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13
I/O2L
P14
I/O1R I/O2R
P15 P16
I/O35R I/O34L TMS
R1 R2 R3
A16R
R4
A13R
R5
A10R
R6
A7R
R7
BE1R BE0R SEMR BUSYR
R8 R9 R10 R11
A6R
R12
A3R
R13
I/ O0L I/ O0R
R14 R15
I/O1L
R16
I /O35L
T1
NC
T2
T RST
T3
NC
T4
A15R
T5
A12R
T6
A9R
T7
BE3R C E0R R/WR
T8 T9 T10
M/ S
T11
A4R
T12
A1R
T13
OPTR
T14
NC
T15
NC
T1 6
,
NC
T CK
NC
A17R(4) A14R
A11R
A8R
BE2R CE1R OER
INT R
A5R
A2R
A0R
NC
NC
5632 drw 02f
NOTES: 1 . All VDD pins must be connected to 2.5V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3 . All VSS pins must be connected to ground supply. 4 . A17X is a NC for IDT70T659. 5 . Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6 . This package code is used to reference the package diagram.
,
3
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