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Part: IDT70V7339S133BC8
Category:
Memory
Description: 512K X 18 Synchronous Bank-switchable Dual-port SRAM
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT70V7339S133BC8 datasheet File size : 398 kB
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Datasheet text preview:
HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
Features:
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IDT70V7339S
x x
x x x
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512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture 64 independent 8K x 18 banks 9 megabits of memory on chip Bank access controlled via bank address pins High-speed data access Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz) (max.) Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports 5ns cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock to data out
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x
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1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz Data input, address, byte enable and control registers Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz Available in a 144-pin Thin Quad Flatpack (TQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1 Due to limited pin count, JTAG is not supported on the 144-pin TQFP package.
Functional Block Diagram
PL/FTL OPTL CLKL ADSL CNTENL REPEATL R/WL CE0L CE1L UBL LBL OEL PL/FTR OPTR CLKR ADSR CNTENR REPEATR R/WR CE0 R CE1 R UBR LBR OER
CONTROL LOGIC
MUX 8Kx18 MEMORY ARRAY (BANK 0) MUX
CONTROL LOGIC
I/O0L -17L
I/O CONTROL
MUX 8Kx18 MEMORY ARRAY (BANK 1) MUX
I/O CONTROL
I/O0 R-17R
A12L A0L BA5L BA4L BA3L BA2L BA1L BA0L
ADDRESS DECODE
ADDRESS DECODE
A12 R A0R BA5R BA4R BA3R BA2R BA1R BA0R
BANK DECODE MUX 8Kx18 MEMORY ARRAY (BANK 63)
BANK DECODE
NOTE: 1 . The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details.
MUX , TDI TDO JTAG TMS TCK TRST
5628 drw 01
DECEMBER 2002
1
DSC 5628/6
©2002 Integrated Device Technology, Inc.
IDT70V7339S High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 8Kx18 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 8Kx18 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7339 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion. The 70V7339 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.
Pin Configuration(1,2,3,4)
1 1 /2 0 /0 1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A 11 A1 2 A1 3 A1 4 A15 A16 A17
IO 9 L
B1
NC
B2
V SS
B3
T DO
B4
NC
B5
B A 3L
B6
A 12L
B7
A 8L
B8
NC
B9
V DD
B10
C LK L CNTEN L A4L
B1 1 B12 B13
A 0L
B14
O PT L
B1 5
NC
B16
V SS
B17
NC
C1
V SS
C2
NC
C3
TD I
C4
B A 4L
C5
B A 0L
C6
A 9L
C7
NC
C8
CE 0L
C9
V SS
C10
A DS L
C1 1
A5L
C12
A 1L
C13
V SS V DDQR I/O 8L
C14 C15 C16
NC
C17
V DDQL I/O9R V DDQR PL/FTL BA 5L B A 1L
D1 D2 D3 D4 D5 D6
A 10L
D7
UB L
D8
C E 1L
D9
V SS
D10
R /W L
D11
A6L
D12
A2L
D13
V DD
D14
I/O8R
D15
NC
D16
V SS
D17
NC
E1
V SS
E2
I/O1 0 L
E3
NC
E4
BA 2L
A 11L
A 7L
LB L
VDD
OE L REPEATL
A3L
VDD
NC
E14
VDDQL I/O 7L
E15 E16
I/O7 R
E17
I/O1 1 L
F1
NC
F2
V DDQR I/O 10R
F3 F4
I/O 6 L
F14
NC
F15
V SS
F16
NC
F17
V DDQL I /O11R
G1 G2
NC
G3
V SS
G4
V SS
G14
I/O6R
G15
NC
G16
V DDQR
G1 7
NC
H1
V SS
H2
I/O 12L
H3
NC
H4
NC
V DDQL I/O5L
H15 H1 6
NC
H17
V DD
J1
NC
J2
V DDQR I/O12R
J3 J4
70V7339BF BF-208(5) 208-Pin fpBGA Top View(6)
H14
V DD
J14
NC
J15
V SS
J16
I/O 5R
J17
VD DQL V DD
K1 K2
V SS
K3
V SS
K4
V SS
K14
VDD
K15
V SS V DDQR
K1 6 K17
I/O 14R
L1
V SS
L2
I/O 13R V SS
L3 L4
I /O3R V DDQL I/O4R
L14 L15 L16
V SS
L17
NC
M1
I/ O14L V DDQR I/O13L
M2 M3 M4
NC
M1 4
I/O 3L
M15
V SS
M1 6
I/O 4 L
M 17
V DDQL
N1
NC
N2
I/O1 5 R V SS
N3 N4
V SS
N1 4
NC
N1 5
I/O2R V DDQR
N1 6 N17
NC
P1
V SS
P2
NC
P3
I/O1 5 L
P4 P5 P6 P7 P8 P9 P10 P11 P1 2 P 13
I/O 1R VD DQL
P14 P1 5
NC
P16
I/O2L
P17
I/O 16R I/O 16L V DDQR
R1 R2 R3
NC
R4
TR ST B A 3R A 12R
R5 R6 R7
A 8R
R8
NC
R9
V DD
R10
CL KR C NTENR A 4R
R11 R12 R13
NC
R14
I/O 1L
R15
V SS
R16
NC
R17
VSS
T1
NC
T2
I/O 17R T CK
T3 T4
B A 4R B A 0R
T5 T6
A 9R
T7
NC
T8
CE 0R
T9
VSS
T10
A DS R
T11
A 5R
T12
A 1R
T13
V SS
T14
V DDQL I/O 0R V DDQR
T15 T16 T17
NC
U1
I/ O17L VDDQL TM S
U2 U3 U4
B A 5R BA 1R
U5 U6
A 10R
U7
UB R
U8
CE 1R
U9
V SS
U10
R /W R
A 6R
U12
A 2R
U1 3
VSS
U14
NC
U15
V SS
U16
NC
U17
V SS
NC
P L/FTR
NC
BA 2R A 11R
A 7R
LB R
V DD
O ER
A 3R
A 0R
V DD
O PT R
NC
I/O0 L
,
5628 drw 02c
NOTES: 1 . All VDD pins must be connected to 3.3V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3 . All VSS pins must be connected to ground supply. 4 . Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5 . This package code is used to reference the package diagram. 6 . This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V7339S High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V7339BC BC-256(5) 256-Pin BGA Top View(6)
11/20/01 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
NC
B1
TDI
B2
NC
B3
BA4L
B4
BA1L A11L
B5 B6
A8L
B7
NC
B8
CE1L
B9
OEL CNTENL
B10 B11
A5L
B 12
A2L
B13
A0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO
C3
BA5L
C4
BA2L
C5
A12L
C6
A9L
C7
UBL
C8
CE0L R/WL REPEATL
C9 C10 C11
A4L
C12
A1L
C13
VDD
C14
NC
C15
NC
C16
NC
D1
I/O9L
D2
VSS
D3
BA3L
D4
BA0L
D5
A10L
D6
A7L
D7
NC
D8
LBL
D9
CLKL ADSL
D10 D11
A6L
D12
A3L
D13
OPTL
D14
NC
D15
I/O8L
D16
NC
E1
I/O9R
E2
NC
E3
PL /FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
NC
E14
NC
E15
I/O8R
E16
I/O10R I/O10L
F1 F2
NC
F3
VDDQL
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
VSS
F9
VSS
F10
VDD
F11
VDD VDDQR
F12 F13
NC
F14
I/O7L
F15
I/O7R
F16
I/O11L
G1
NC
G2
I/O11R VDDQL
G3 G4
VDD
G5
VSS
G6
VS S
G7
VS S
G8
VSS
G9
VSS
G10
VSS
G11
VDD VDDQR I/O6R
G12 G13 G14
NC
G15
I/O6L
G16
NC
H1
NC
H2
I/O12L VDDQR
H3 H4
VSS
H5
VSS
H6
VSS
H7
VS S
H8
VSS
H9
VSS
H10
VSS
H11
VS S
H12
VDDQL I/O5L
H13 H14
NC
H15
NC
H16
NC
J1
I/O12R
J2
NC
J3
VDDQR VSS
J4 J5
VSS
J6
VS S
J7
VS S
J8
VSS
J9
VSS
J10
VSS
J11
VS S
J12
VDDQL
J13
NC
J14
NC
J15
I/O5R
J16
I/O13L I/O14R I/O13R VDDQL
K1 K2 K3 K4
VSS
K5
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VDDQR I/O4R I/O3R
K13 K14 K15
I/O4L
K16
NC
L1
NC
L2
I/O14L VDDQL
L3 L4
VSS
L5
VSS
L6
VS S
L7
VS S
L8
VSS
L9
VSS
L10
VSS
L11
VS S
L12
VDDQR
L13
NC
L14
NC
L15
I/O3L
L16
I/O15L
M1
NC
M2
I/O15R VDDQR
M3 M4
VDD
M5
VSS
M6
VSS
M7
VS S
M8
VSS
M9
VSS
M10
VSS
M11
VDD
M12
VDDQL I/O2L
M13 M14
NC
M15
I/O2R
M16
I/O16R I/O16L
N1 N2
NC
N3
VDDQR
N4
VDD
N5
VDD
N6
VS S
N7
VSS
N8
VSS
N9
VSS
N10
VDD
N11
VDD
N12
VDDQL I/O1R
N13 N14
I/O1L
N15
NC
N16
NC
P1
I/O17R
P2
NC
P3
PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P4 P5 P6 P7 P8 P9 P10 P11 P12
VDD
P13
NC
P14
I/O0R
P15
NC
P16
NC
R1
I/O17L TMS
R2 R3
BA3R BA0R
R4 R5
A10R
R6
A7R
R7
NC
R8
LBR
R9
CLKR ADSR
R10 R11
A6R
R12
A3R
R13
NC
R14
NC
R15
I/O0L
R16
NC
T1
NC
T2
TRST BA5R BA2R
T3 T4 T5
A12R
T6
A9R
T7
UBR
T8
CE0R
T9
R/WR REPEATR
T10 T11
A4R
T1 2
A1R
T13
OPTR
T14
NC
T15
NC
T16
,
NC
TCK
NC
BA4R
BA1R
A11R
A8R
NC
CE1R
OER CNTENR
A5R
A2R
A0R
NC
NC
5628 drw 02d
NOTES: 1 . All VDD pins must be connected to 3.3V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3 . All VSS pins must be connected to ground supply. 4 . Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5 . This package code is used to reference the package diagram. 6 . This text does not indicate orientation of the actual part-marking.
,
6.42 3
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