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Part: IDT7132SA20L48B
Category:
Interface and Interconnect
-> Multi-Ports
Description: High-speed 2K X 8 Dual-port Static RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT7132SA20L48B datasheet File size : 398 kB
Request For quote: Find where to buy IDT7132SA20L48B
Datasheet text preview:
HIGH SPEED 2K x 8 DUAL PORT STATIC RAM
Features
High-speed access Military: 25/35/55/100ns (max.) Commercial: 20/25/35/55/100ns (max.) Low-power operation IDT7132/42SA Active: 325mW (typ.) Standby: 5mW (typ.) IDT7132/42LA Active: 325mW (typ.) Standby: 1mW (typ.)
x
IDT7132SA/LA IDT7142SA/LA
x
x x x x x
x
x x
MASTER IDT7132 easily expands data bus width to 16-or-more bits using SLAVE IDT7142 On-chip port arbitration logic (IDT7132 only) BUSY output flag on IDT7132; BUSY input on IDT7142 Battery backup operation --2V data retention (LA only) TTL-compatible, single 5V ±10% power supply Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC packages Military product compliant to MIL-PRF-38535 QML Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/OOL-I/O7L
I/O Control
I/O Control
I/OOR-I/O7R
m
BUSYL(1,2) A10L A0L Address Decoder
11
BUSYR(1,2) MEMORY ARRAY
11
Address Decoder
A10R A0R
CEL OEL R/WL
ARBITRATION LOGIC
CER OER R/WR
2692 drw 01
NOTES: 1 . IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT7142 (SLAVE): BUSY is input. 2 . Open drain output: requires pullup resistor of 270.
JANUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC-2692/15
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and l/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery. The IDT7132/7142 devices are packaged in a 48-pin sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
CEL R/WL BUSYL A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 48 2 47 3 46 4 45 5 44 6 43 7 IDT7132/ 42 8 7142 41 9 P or C 40 10 39 11 P48-1(4) 38 12 37 & 13 C48-2(4) 36 14 35 15 48-Pin 34 16 DIP 33 17 Top 32 18 View(5) 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC CER R/WR BUSYR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R
2692 drw 02
VCC CER R/WR BUSYR A10R
BUSYL R/WL CEL
A0L OEL A10L
INDEX
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L
654 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
48 47 46 45 44 43 42 41 40 39 IDT7132/42L48 or F L48-1(4) 38 & 37 F48-1(4) 36 48-Pin LCC/ Flatpack (5) 35 Top View 34 33 32 31 22 23 24 25 26 27 28 29 30 1
32
OER
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R
,
,
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3 . P48-1 package body is approximately .55 in x 2.43 in x .18 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Capacitance(1) (TA = +25°C,f = 1.0MHz)
Symbol CIN COUT Param eter Inp ut Capacitance Outp ut Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 11 11 Unit pF pF
2692 tbl 00
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 3V to 0V.
2
I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R
2692 drw 03
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
INDEX
76 54 32 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R
2692 drw 04
IDT7132/42J J52-1(4) 52-Pin PLCC Top View(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Te rminal Voltage with Respect to GND Te mp e rature Und e r Bias Storag e Te mp e rature DC Output Curre nt Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
I/O4L I/O5L I/O6L I/O7L N/C GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
Grade Military
Recommended Operating Temperature and Supply Voltage(1,2)
Ambient Temperature -55 C to+125 C 0 C to +70 C -40 C to +85 C
O O O O O O
R/WR BUSYR N/C A10R
A0L OEL A10L N/C BUSYL
Pin Configurations(1,2,3) (con't.)
R/WL CEL VCC CER
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2692 tbl 02
TBIAS TS TG IOUT
-55 to +125 -65 to +150 50
-65 to +135 -65 to +150 50
o
C C
Co mme rcial Ind ustrial
o
mA
2692 tbl 01
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Mi n. 4. 5 0 2. 2 -0. 5(1) Typ. 5. 0 0
____
Max. 5. 5 0 6. 0
(2)
Unit V V V V
2692 tbl 03
____
0. 8
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
3 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5,8) (VCC = 5.0V ± 10%)
7132X20(2) 7142X20(2) Com 'l Only Sym bol ICC Param eter Dy namic Operating Current (Bo th Ports Active) Test Condition C EL = CER = VIL, Outp uts Disabled f = fMAX(3) Version COM'L MIL & IND COM'L MIL & IND IS B2 Stand b y Current (One Port - TTL Le v e l Inputs) C E"A " = VIL and CE"B" = VIH (6) Ac tiv e Port Outputs Disabled f=fMAX(3) COM'L MIL & IND COM'L MIL & IND IS B4 Full Standby Current (One Port - All CMOS Level Inputs) C E"A " VCC -0.2V(6) VIN > VCC - 0.2V or VIN < 0.2V Ac tiv e Port Outputs Disabled f = fMAX(3) COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 110 110
____ ____
7132X25(7) 7142X25(7) Com 'l & Military Typ. 110 110 110 110 30 30 30 30 65 65 65 65 1.0 0.2 1.0 0.2 60 60 60 60 Max. 220 170 280 220 65 45 80 60 150 115 160 125 15 5 30 10 145 105 155 115
7132X35 7142X35 Com 'l & Military Typ. 80 80 80 80 25 25 25 25 50 50 50 50 1.0 0.2 1.0 0.2 45 45 45 45 Max. 165 120 230 170 65 45 80 60 125 90 150 115 15 4 30 10 110 85 145 105
2 692 tbl 04a
Max. 250 200
____ ____
Unit mA
IS B1
Stand b y Current (Bo th Ports - TTL Le v e l Inputs)
C EL = CER = VIH, f = fMAX(3)
30 30
____ ____
65 45
____ ____
mA
65 65
____ ____
165 125
____ ____
mA
IS B3
Full Standby Current (Both P o r ts - All CMOS Level Inputs)
C EL and CER > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
1.0 0.2
____ ____
15 5
____ ____
mA
60 60
____ ____
155 115
____ ____
mA
7132X55 7142X55 Com 'l & Military Sym bol ICC Param eter Dy namic Operating Curre nt (Bo th Ports Active) C EL = CER = VIL, Outp uts Disabled f = fMAX(3) Test Condition Version COM'L MIL & IND COM'L MIL & IND IS B2 Stand b y Current (One Port - TTL Le v e l Inputs) C E"A " = VIL and CE"B" = VIH (6) Ac tiv e Port Outputs Disabled f=fMAX(3) COM'L MIL & IND COM'L MIL & IND IS B4 Full Standby Current (One Port - All CMOS Level Inputs) C E"A " VCC -0.2V(6) VIN > VCC - 0.2V or VIN < 0.2V Ac tiv e Port Outputs Disabled f = fMAX(3) COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 Max. 155 110 190 140 65 35 65 45 110 75 125 90 15 4 30 10 100 70 110 85
7132X100 7142X100 Com 'l & Military Typ. 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 Max. 155 110 190 140 55 35 65 45 110 75 125 90 15 4 30 10 95 70 110 80
2692 tbl 04b
Unit mA
IS B1
Stand b y Current (Bo th Ports - TTL Le v e l Inputs)
C EL = CER = VIH, f = fMAX(3)
mA
mA
IS B3
Full Standby Current (Bo th Ports - All CMOS Level Inputs)
C EL and CER > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
mA
mA
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC Package only 3. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7. Not available in DIP packages. 8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
4
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
7132SA 7142SA Symbol |ILI| |ILO| V OL V OL VOH Parameter Inp ut Leakage Current
(1)
7132LA 7142LA Mi n.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC VCC = 5.5V, C E = VIH, VOUT = 0V to VCC IOL = 4mA IOL = 16mA IOH = -4mA
Mi n.
___
Max. 10 10 0.4 0.5
___
Max. 5 5
Unit µA
Outp ut Leakage Current Outp ut Low Voltage Op e n Drain Output Lo w Voltage (BUSY, INT) Outp ut High Voltage
___
___
µA
___ ___ ___ ___
0.4 0.5
V V
2.4
2.4
___
V
2692 tbl 05
NOTE: 1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2.0V C E > VCC -0.2V VIN > VCC -0.2V or tCDR(3) tR(3) Chip Deselect to Data Retention Time Op e ratio n Recovery Time VIN < 0.2V Mil. & Ind. Co m'l. Test Condition Min. 2.0
___
Typ.(1)
___
Max.
___
Unit V µA µA ns ns
2692 tbl 06
100 100
___
4000 1500
___
___
0 tRC(2)
___
___
NOTES: 1. VCC = 2V, TA = +25°C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
4.5V tCDR
4.5V tR
CE VIH
VDR VIH
2692 drw 05 ,
5 6.42
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