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Details, datasheet, quote on part number:IDT71342LA45PF
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Datasheet text preview:
HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
Features
x
IDT71342SA/LA
x
High-speed access Commercial: 20/25/35/45/55/70ns (max.) Industrial: 25/35/55ns (max.) Low-power operation IDT71342SA Active: 700mW (typ.) Standby: 5mW (typ.) IDT71342LA Active: 700mW (typ.) Standby: 1mW (typ.)
x x
x x x x
Fully asynchronous operation from either port Full on-chip hardware support of semaphore signalling between ports Battery backup operation--2V data retention (LA only) TTL-compatible; single 5V (±10%) power supply Available in plastic packages Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
R/WL CEL R/WR CER
OEL I/O CONTROL I/O CONTROL
OER
I/O0L- I/O7L
I/O0R - I/O7R
MEMORY ARRAY
SEMAPHORE LOGIC SEML ADDRESS DECODER ADDRESS DECODER SEMR
A0L- A11L
A0R- A11R
2721 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC 2621/12
IDT71342SA/LA High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Description
The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full on-chip hardware support of semaphore signalling between the two ports. The IDT71342 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. To assist in arbitrating between ports, a fully independent semaphore logic block is provided. This block contains unassigned flags which can be accessed by either side; however, only one side can control the flag at any
time. An automatic power down feature, controlled by CE and SEM, permits the on-chip circuitry of each port to enter a very low standby power mode (both CE and SEM HIGH). Fabricated using IDT's CMOS high-performance technology, this device typically operates on only 700mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW from a 2V battery. The device is packaged in either a 64-pin TQFP or a 52-pin PLCC.
Pin Configurations(1,2,3)
INDEX
765 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20
43
2
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7 R
IDT71342J J52-1(4) 52-Pin PLCC Top View(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O5L
N/C GND
I/O0R I/O1R I/O2R
I/O4R I/O5R
I/O3R
I/O6R
I/O4L
I/O6L I/O7L
R/WR SEMR A11R A10R
SEML R/WL CEL
VCC CER
OEL A10L
A11L
A0 L
2721 drw 02
INDEX OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C A10L A11L SEML R/WL CEL VCC N/C CER R/WR SEM R A11R A10R N/C N/C
NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3 . J52 package body is approximately .79 in x .79 in x .17 in. PN64 package body is approximately 14mm x 14mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C N/C GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
71342PF PN64-1(4) 64-Pin TQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R
2721 drw 03
6.42 2
IDT71342SA/LA High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Te rminal Voltage with Respect to GND Te mp e rature Und e r Bias Sto rag e Te mp e rature Po we r Diss ip atio n DC Output Curre nt Com merci al & Industrial -0. 5 to +7.0 Uni t V
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Co mme rc ial Ambi ent Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
2721 tbl 03
TBIAS TSTG PT(3) IOUT
-55 to +125 -65 to +150 1.5 50
o
C C
Ind ustrial
o
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature.
W mA
2721 tbl 01
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10 ns maximum, and is limited to Vcc +10%.
Recommended DC Operating Conditions
Symbol VCC GND VIH V IL Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage M in . 4. 5 0 2. 2 -0.5(1) Typ. 5. 0 0
____
Max. 5. 5 0 6. 0(2) 0. 8
Unit V V V V
2721 tbl 04
____
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol CIN COUT Parameter Inp ut Capacitance Outp ut Capacitance Conditions(2) VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF
2721 tbl 02
NOTES: 1 . VIL (min.) > -1.5V for pulse width less than 10ns. 2 . VTERM must not exceed Vcc + 10%.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage (VCC = 5V ± 10%)
71342SA Symbol |ILI| |ILO| V OL Param eter Input Leakage Current
(1)
71342LA Min.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC C E = VIH, VOUT = 0V to VCC IOL = 6mA IOL = 8mA
Min.
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit µA µA V V V
2721 tbl 05
Output Leakage Current Output Low Voltage
___
___
___
___
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
3 6.42
IDT71342SA/LA High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
71342X20 Com 'l Only Sym bol ICC Param eter Dynamic Operating Current (Bo th Ports Active) Test Condition C E = VIL, Outp uts Disabled SEM = Don't Care f = fMAX(3) C EL and CER = VIH SEML = SEMR > VIH f = fMAX(3) Versi on COM' L IND COM' L IND COM' L IND COM' L IND COM' L IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ .(2) 170 170
____ ____
71342X25 Com 'l & Ind Typ . (2) 160 160 160 160 25 25 25 25 95 95 95 95 1. 0 0. 2 1. 0 0. 2 95 95 95 95 Max. 280 240 310 260 80 50 100 80 180 150 210 170 15 4. 0 30 10 170 120 210 190
71342X35 Com 'l & Ind Typ . (2) 150 150 150 150 25 25 25 25 85 85 85 85 1. 0 0. 2 1. 0 0. 2 85 85 85 85 Max. 260 200 300 250 75 45 75 55 170 140 200 160 15 4. 0 30 10 150 110 190 130
2721 tbl 06a
Max. 280 240
____ ____
Uni t mA
ISB1
Stand b y Current (Bo th Ports - TTL Le v e l Inputs)
25 25
____ ____
80 80
____ ____
mA
ISB2
Stand b y Current (One Port - TTL Le v e l Inputs)
C E"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fMAX(3)
105 105
____ ____
180 150
____ ____
mA
ISB3
Full Standby Current (Both Po rts CMOS Level Inputs)
Bo th Ports CEL and C ER > VCC - 0.2V, VIN > VCC - 0.2V or VIN VCC - 0.2V f = 0(3) One Port CE"A" or C E"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN VCC - 0.2V Active Port Outputs Disabled, f = fMAX(3)
1. 0 0. 2
____ ____
15 4. 5
____ ____
mA
ISB4
Full Standby Current (One Port CMOS Level Inputs)
105 105
____ ____
170 130
____ ____
mA
71342X45 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled SEM = Don't Care f = fMAX(3) CEL and CER = VIH SEML = SEMR > VIH f = fMAX(3) Versi on COM' L IND COM' L IND COM' L IND COM' L IND COM' L IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ.(2) 140 140
____ ____
71342X55 Com'l & Ind Typ. (2) 140 140 140 140 25 25 25 25 75 75 75 75 1. 0 0. 2 1. 0 2. 0 75 75 75 75 Max. 240 200 270 220 70 40 70 50 160 130 180 150 15 4. 0 30 10 150 100 170 120
71342X70 Com'l Only Typ.(2) 140 140
____ ____
Max. 240 200
____ ____
Max. 240 200
____ ____
Uni t mA
ISB 1
Stand by Current (Both Ports - TTL Lev el Inputs)
25 25
____ ____
70 40
____ ____
25 25
____ ____
70 40
____ ____
mA
ISB 2
Stand by Current (One Port - TTL Lev el Inputs)
CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fMAX(3)
75 75
____ ____
160 130
____ ____
75 75
____ ____
160 130
____ ____
mA
ISB 3
Full Standby Current (Both Ports CMOS Level Inputs)
Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN VCC - 0.2V f = 0(3) One Port CE"A" or CE"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN VCC - 0.2V Active Port Outputs Disabled, f = fMAX(3)
1. 0 0. 2
____ ____
15 4. 0
____ ____
1. 0 0. 2
____ ____
15 4. 0
____ ____
mA
ISB 4
Full Standby Current (One Port CMOS Level Inputs)
75 75
____ ____
150 100
____ ____
75 75
____ ____
150 100
____ ____
mA
2721 tbl 06b
NOTES: 1. 'X' in part number indicates power rating (SA or LA). 2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested. 3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
6.42 4
IDT71342SA/LA High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Data Retention Characteristics
Symbol VDR ICCDR tCDR (3) tR
(3)
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Param eter VCC for Data Retention Data Retention Current Chip Dese lec t to Data Retention Time Ope ratio n Recovery Time VCC = 2V, CE > VHC SEM > VHC VIN > VHC or < VLC Test Condition
___
Min. 2.0
Typ.(1)
Max.
___
Unit V µA ns ns
2721 tbl 07
COM'L. & IND.
___
100
___
1500
___
0 tRC
(2)
___
___
NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested.
Data Rention Waveform
VCC 4.5V tCDR CE VIH
DATA RETENTION MODE VDR > 2V VDR 4.5V tR VIH
2721 drw 04
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Fi g ures 1 and 2
2721 tbl 08
+5V 1250 DATAOUT 775 30pF
2721 drw 05 ,
+5V 1250 DATAOUT 775 5pF *
, 2721 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig
5 6.42
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