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Part: IDT7140SA55PI
Category:
Interface and Interconnect
-> Multi-Ports
Description: 1K X 8 Dual-port RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT7140SA55PI datasheet File size : 398 kB
Request For quote: Find where to buy IDT7140SA55PI
Datasheet text preview:
HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
Features
x
IDT7130SA/LA IDT7140SA/LA
x
x
High-speed access Military: 25/35/55/100ns (max.) Industrial: 55/100ns (max.) Commercial: 20/25/35/55/100ns (max.) Low-power operation IDT7130/IDT7140SA -- Active: 550mW (typ.) -- Standby: 5mW (typ.) IDT7130/IDT7140LA -- Active: 550mW (typ.) -- Standby: 1mW (typ.) MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140
x x x x x x x x
x
On-chip port arbitration logic (IDT7130 Only) BUSY output flag on IDT7130; BUSY input on IDT7140 INT flag for port-to-port communication Fully asynchronous operation from either port Battery backup operation2V data retention (LA only) TTL-compatible, single 5V ±10% power supply Military product compliant to MIL-PRF-38535 QML Industrial temperature range (40°C to +85°C) is available for selected speeds Available in 48-pin DIP and LCC, 52-pin PLCC, and 64-pin STQFP and TQFP
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL
(1,2)
I/O Control
I/O0R-I/O7R
,
BUSYR Address Decoder
10
(1,2)
A9L A0L
MEMORY ARRAY
10
Address Decoder
A9R A0R
CEL OEL R/WL
ARBITRATION and INTERRUPT LOGIC
CER OER R/WR
INTL
(2)
INTR
2689 drw 01
(2)
NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor.
JUNE 2000
1
DSC-2689/10
©2000 Integrated Device Technology, Inc.
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance tech-nology, these devices typically operate on only 550mW of power. Lowpower (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200µW from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
CEL R/WL BUSYL INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 IDT7130/40 41 9 P or C ) 40 (4 10 P48-1 39 & 11 C48-2(4) 38 12 48-Pin 37 13 DIP (5) 36 14 Top View 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC CER R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R INDEX I/O6R I/O5R I/O4R I/O3R A1L I/O2R A2L I/O1R I/O0R A3L
,
2689 drw 02
OEL INTL BUSYL
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. P48-1 package body is approximately .55 in x .61 in x .19 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L
654 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
48 47 46 45 44 43 42 41 40 39 IDT7130/40L48 or F (4) 38 L48-1 & 37 F48-1(4) 36 48-Pin LCC/ Flatback 35 Top View(5) 34 33 32 31 22 23 24 25 26 27 28 29 30 1
32
R/WL CEL VCC CER
R/WR BUSYR INTR OER
A0L
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R
,
2
I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R
2689 drw 03
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
INDEX
76 5432 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R
2689 drw 04
IDT7130/40J J52-1(4) 52-Pin PLCC Top View(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
INDEX OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C N/C INTL BUSYL R/WL CEL VCC VCC CER R/WR BUSYR INTR N/C N/C N/C
I/O4L I/O5L I/O6L I/O7L N/C GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
CER R/WR BUSYR INTR N/C
A0L OEL N/C INTL BUSYL R/WL CEL VCC
Pin Configurations(1,2,3) (con't.)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT7130/40TF or PF PP64-1 & PN64-1(4) 64-Pin STQFP 64-Pin TQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R
, 2689 drw 05
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
3
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rati ng Terminal Voltage with Respect to GND Tempe rature Und e r Bias Sto rag e Tempe rature DC Output Current Commercial & Industrial -0. 5 to +7.0 Mi litary -0. 5 to +7.0 Unit V
Recommended DC Operating Conditions
Sym bol VCC GND Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Mi n. 4.5 0 2.2 -0. 5(1) Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Uni t V V V V
2689 tbl 02
TB IA S TS TG IO UT
-55 to +125 -65 to +150 50
-65 to +135 -65 to +150 50
o
C C
VIH V IL
o
0.8
mA
26 89 tbl 01
NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to Vcc + 10%.
Recommended Operating Temperatur e and Supply Voltage(1,2)
Grade Military Commercial Ambient Temperature -55OC to +125OC 0 C to +70 C -40 C to +85 C
O O O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2689 tbl 03
Capacitance
Symbol CIN COUT
(TA = +25°C, f = 1.0MHz)
Conditions VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
2689 tbl 05
Industrial
STQFP and TQFP Packages Only
Parameter(1) Inp ut Capacitance Outp ut Capacitance
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (VCC = 5.0V ± 10%)
7130SA 7140SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current
(1) (1)
7130LA 7140LA Min .
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC VCC - 5.5V, C E = VIH, VOUT = 0V to VCC IOL = 4mA IOL = 16mA IOH = -4mA
Min .
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit µA µA V V V
2689 tbl 04
Outp ut Leakage Current
___
___
Outp ut Low Voltage (I/O0-I/O7) Open Drain Output Lo w Voltage (BUSY, INT) Outp ut High Voltage
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V leakages are undefined.
4
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5,7) (VCC = 5.0V ± 10%)
7 1 3 0 X 2 0 (2) 7 1 4 0 X 2 0 (2) C o m ' l Only S ym b ol IC C P ar am eter D y n a m i c O p e r a ti n g C u rr e n t ( B o th P o r ts A c ti v e ) T e s t Con d i t i o n CEL and CER = V I L, O u tp u ts Disab l e d f = fMAX (3) V e rs i o n CO M 'L M IL & IN D CO M 'L M IL & IN D IS B 2 S ta n d b y Curre n t ( O n e P o r t - TTL L e v e l Inp u ts ) CE"A " = V I L and CE"B" = VIH (6) A c ti v e P o r t O u tp u ts D i s a b le d , f= fM A X (3) CO M 'L M IL & IN D CO M 'L M IL & IN D CO M 'L M IL & IN D SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA T yp . 11 0 11 0
____ ____
71 30X 2 5 71 40X 2 5 C o m 'l & M i l i ta ry T yp . 11 0 11 0 11 0 11 0 30 30 30 30 65 65 65 65 1. 0 0. 2 1. 0 0. 2 60 60 60 60 M a x. 22 0 17 0 28 0 22 0 65 45 80 60 15 0 11 5 16 0 12 5 15 5 30 10 14 5 10 5 15 5 11 5
71 30X 3 5 71 40X 3 5 C o m 'l & M i l i ta ry T yp . 11 0 11 0 11 0 11 0 25 25 25 25 50 50 50 50 1. 0 0. 2 1. 0 0. 2 45 45 45 45 M a x. 16 5 12 0 23 0 17 0 65 45 80 60 12 5 90 15 0 11 5 15 4 30 10 11 0 85 14 5 10 5
2 6 89 tb l 06a
M a x. 25 0 20 0
____ ____
Unit mA
IS B 1
S ta n d b y Curre n t ( B o th P o r ts - TTL L e v e l Inp u ts )
CEL and CER = V IH f = fMAX (3)
30 30
____ ____
65 45
____ ____
mA
65 65
____ ____
16 5 12 5
____ ____
mA
IS B 3
F u l l S ta n d b y Curre n t ( B o th P o r ts C M O S Le v e l Inp u ts )
CEL and CER > V C C - 0.2V, V IN > V C C - 0.2V o r V IN VCC - 0.2V (6) V IN > V C C - 0.2V o r V IN < 0.2V A c ti v e P o r t O u tp u ts D is a b l e d , f = fMAX (3)
1. 0 0. 2
____ ____
15 5
____ ____
mA
IS B 4
F u l l S ta n d b y Curre n t (O n e P o rt C M O S Le v e l Inp u ts )
60 60
____ ____
15 5 11 5
____ ____
mA
71 30X 5 5 71 40X 5 5 C o m ' l , In d & M il itar y S ym b ol IC C P ar am eter D y n a m i c O p e r a ti n g C u rr e n t ( B o th P o r ts A c ti v e ) CEL and CER = V I L, O u tp u ts Disab l e d f = fMAX (3) T e s t Con d i t i o n V e rs i o n CO M 'L M IL & IN D CO M 'L M IL & IN D IS B 2 S ta n d b y Curre n t ( O n e P o r t - TTL L e v e l Inp u ts ) CE"A " = V I L and CE"B" = VIH (6) A c ti v e P o r t O u tp u ts D is a b l e d , f= fM A X (3) CO M 'L M IL & IN D CO M 'L M IL & IN D CO M 'L M IL & IN D SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA T yp . 11 0 11 0 11 0 11 0 20 20 20 20 40 40 40 40 1. 0 0. 2 1. 0 0. 2 40 40 40 40 M a x. 15 5 11 0 19 0 14 0 65 35 65 45 11 0 75 12 5 90 15 4 30 10 10 0 70 11 0 85
71 30X 1 00 71 40X 1 00 C o m ' l , In d & M il itar y T yp . 11 0 11 0 11 0 11 0 20 20 20 20 40 40 40 40 1. 0 0. 2 1. 0 0. 2 40 40 40 40 M a x. 15 5 11 0 19 0 14 0 55 35 65 45 11 0 75 12 5 90 15 4 30 10 95 70 11 0 80 mA mA mA mA Unit mA
IS B 1
S ta n d b y Curre n t ( B o th P o r ts - TTL L e v e l Inp u ts )
CEL and CER = V IH f = fMAX (3)
IS B 3
F u l l S ta n d b y Curre n t ( B o th P o r ts C M O S Le v e l Inp u ts )
CEL and CER > V C C - 0.2V, V IN > V C C - 0.2V o r V IN VCC - 0.2V (6) V IN > V C C - 0.2V o r V IN < 0.2V A c ti v e P o r t O u tp u ts D is a b l e d , f = fMAX (3)
IS B 4
F u l l S ta n d b y Curre n t (O n e P o rt C M O S Le v e l Inp u ts )
2 689 tb l 0 6b NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC and TQFP packages only. 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7. Industrial temperature: for other speeds, packages and powers contact your sales office.
5
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