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Part: IDT71421
Category:
Memory
-> Multiport->16K
Description: a High Speed 2kx8 Dual-port Static RAM With Interrupts
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT71421 datasheet File size : 398 kB
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Datasheet text preview:
IDT71321SA/LA HIGH SPEED IDT71421SA/LA 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
Features
x
x
x
High-speed access Commercial: 20/25/35/55ns (max.) Industrial: 55ns (max.) Low-power operation IDT71321/IDT71421SA -- Active: 325mW (typ.) -- Standby: 5mW (typ.) IDT71321/421LA -- Active: 325mW (typ.) -- Standby: 1mW (typ.) Two INT flags for port-to-port communications
x
x x x x x x x
MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SLAVE IDT71421 On-chip port arbitration logic (IDT71321 only) BUSY output flag on IDT71321; BUSY input on IDT71421 Fully asynchronous operation from either port Battery backup operation 2V data retention (LA only) TTL-compatible, single 5V ±10% power supply Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL A10L A0L
(1,2)
I/O Control
I/O0R-I/O7R
BUSYR Address Decoder
11
(1,2)
MEMORY ARRAY
11
Address Decoder
A10R A0R
CEL OEL R/WL
ARBITRATION and INTERRUPT LOGIC
CER OER R/WR
INTL
(2)
INTR
2691 drw 01
(2)
NOTES: 1 . IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT71421 (SLAVE): BUSY is input. 2 . Open drain output: requires pullup resistor of 270.
MARCH 1999
1
©1999 Integrated Device Technology, Inc. DSC-2691/8
1
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit DualPort Static RAM or as a "MASTER" Dual-Port Static RAM together with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM approach in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery. The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs, 64-pin TQFPs, and 64-pin STQFPs.
INDEX A1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
87 6 5 4 3 2 1 52 51 50 49 48 47 46 45 9 10 44 11 43 12 42 IDT71321/421J 13 41 J52-1(4) 14 40 15 39 PLCC 16 38 Top View(5) 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33
R/W L CE L V CC CER R/W R BUSYR INTR A10R
OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O7R
2691 drw 02
Pin Configurations(1,2,3)
INT L BUSYL A 0L OE L A10L
INDEX OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C A10L INTL BUSYL R/WL CEL VCC VCC CER R/WR BUSYR INTR A10R N/C N/C
,
I/O 4L I/O 5L I/O 6L I/O 7L
I/O 0R I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R
NC GND
2 6.42
I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
NOTES: 1. All VCC pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . J52-1 package body is approximately .75 in x .75 in x .17 in. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT71321/421PF or TF PN64-1 / PP64-1(4) 64-Pin TQFP 64-Pin STQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R
, 2691 drw 03
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Capacitance(1)
Symbol CIN COUT
(TA = +25°C, f = 1.0MHz) TQFP Only
Parameter Inp ut Capacitance Outp ut Capacitance Conditions(2) VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF
2691 tbl 00
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Commerc ial Ind ustrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
2691 tbl 02
NOTES: 1 . This parameter is determined by device characterization but is not production tested. 2 . 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
NOTES: 1 . This is the parameter TA. 2 . Industrial temperature: for specific speeds, packages and powers contact your sales office.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Te rminal Voltage with Respect to GND Temp erature Unde r Bias Sto rag e Temp erature DC Output Curre nt Commercial & Industrial -0.5 to +7.0 Unit V
Recommended DC Operating Conditions
Sym bol V CC GND Param eter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Min. 4. 5 0 2. 2 -0.5(1) Typ. 5. 0 0
____
Max. 5. 5 0 6. 0
(2)
Uni t V V V V
2691 tbl 03
TBIA S TSTG IOUT
-55 to +125 -55 to +125 50
o
C C
V IH V IL
____
o
0. 8
mA
2691 tbl 01
NOTES: 1 . VIL (min.) = -1.5V for pulse width less than 10ns. 2 . VTERM must not exceed Vcc + 10%.
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to VCC + 10%.
3 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,4,6) (VCC = 5.0V ± 10%)
71321X 20 71421X 20 Co m 'l Only S ym b ol ICC P aram eter D y n am ic Op e rati n g C u rre n t (B o th Po rts Active ) CEL and CER = VIL, O u tp u ts Ope n f = fMAX(2) Test Condition V ersi o n CO M ' L IN D CO M ' L IN D IS B 2 S ta nd b y Curre nt (O n e Po rt - TTL L e v e l Inp uts ) CE"A " = VIL and CE"B" = VIH (5) A c ti v e Po rt Outputs Op e n , f= fM A X(2) CO M ' L IN D CO M ' L IN D CO M ' L IN D SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA T yp . 110 110
____ ____
71321X 25 71421X 25 Co m 'l Only T yp . 110 110
____ ____
M ax. 2 50 2 00
____ ____
M ax. 2 20 1 70
____ ____
U ni t mA
IS B 1
S ta nd b y Curre nt (B o th Po rts - TTL L e v e l Inp uts )
CEL and CER = VIH f = fMAX(2)
30 30
____ ____
65 45
____ ____
30 30
____ ____
65 45
____ ____
mA
65 65
____ ____
1 65 1 25
____ ____
65 65
____ ____
1 50 115
____ ____
mA
IS B 3
F ul l S tan d b y Current (B o th Po rts C M O S Leve l Inputs)
CEL and CER > VCC - 0.2V, V IN > VCC - 0.2V o r V IN VCC - 0.2V (5) V IN > VCC - 0.2V o r V IN < 0.2V A c ti v e Po rt Outputs Op e n , f = fMAX(2)
1. 0 0. 2
____ ____
15 5
____ ____
1. 0 0. 2
____ ____
15 5
____ ____
mA
IS B 4
F ul l S tan d b y Current (O n e Po rt C M O S Leve l Inputs)
60 60
____ ____
1 55 115
____ ____
60 60
____ ____
1 45 1 05
____ ____
mA
2 691 tbl 04a
71321X 35 71421X 35 Co m 'l Only S y m b ol ICC P aram eter D y n am i c Ope rati ng C u rre nt (B o th Po rts Active) CEL and CER = VIL, O u tp u ts Op e n f = fMAX(2) Test Condition V ersi on CO M ' L IN D CO M ' L IN D IS B 2 S ta nd b y Curre nt (O n e Po rt - TTL L e v e l Inp uts ) CE"A " = VIL and CE"B" = VIH (5) A c ti v e P o rt Outp uts Ope n, f= fM A X(2) CO M ' L IN D CO M ' L IN D CO M ' L IN D SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA T yp . 80 80
____ ____
71321X 55 71421X 55 Co m 'l & Ind T yp . 65 65 65 65 20 20 20 20 40 40 40 40 1. 0 0. 2 1. 0 0. 2 40 40 40 40 M ax. 1 55 110 1 90 1 40 65 35 65 45 110 75 1 25 90 15 4 30 10 1 00 70 110 85
2691 tbl 04b
M ax. 1 65 1 20
____ ____
Un i t mA
IS B 1
S ta nd b y Curre nt (B o th Po rts - TTL L e v e l Inp uts )
CEL and CER = VIH f = fMAX(2)
25 25
____ ____
65 45
____ ____
mA
50 50
____ ____
1 25 90
____ ____
mA
IS B 3
F ul l S tan d b y Curre nt (B o th Po rts C M O S Level Inp uts )
CEL and CER > VCC - 0.2V, V IN > VCC - 0.2V o r V IN VCC - 0.2V (5) V IN > VCC - 0.2V o r V IN < 0.2V A c ti v e P o rt Outp uts Ope n, f = fMAX(2)
1. 0 0. 2
____ ____
15 4
____ ____
mA
IS B 4
F ul l S tan d b y Curre nt (O n e Po rt C M O S Level Inp uts )
45 45
____ ____
110 85
____ ____
mA
NOTES: 1 . 'X' in part numbers indicates power rating (SA or LA). 2 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 3 . f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4 . Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ) 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 6 . Industrial temperature: for other speeds, packages and powers contact your sales office.
4 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (VCC = 5.0V ± 10%)
71321SA 71421SA Symbol |ILI| |ILO| V OL V OL VOH Param eter Input Leakage Current
(1) (1)
71321LA 71421LA Min.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC C E = VIH, VOUT = 0V to VCC, VCC - 5.5V IOL = 4mA IOL = 16mA IOH = -4mA
Min.
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit µA µA V V V
2691 tbl 05
Output Leakage Current
___
___
Output Low Voltage (I/O0-I/O7) Op en Drain Output Lo w Voltage (BUSY/INT) Output High Voltage
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol VDR ICCDR Param eter VCC for Data Retention Data Retention Current VCC = 2.0V, CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V tCDR (3) tR(3) Chip Deselect to Data Retention Time Ope ratio n Recovery Time COM'L IND Test Condition Min. 2.0
____
Typ. (1)
____
Max. 0 1500 4000
____
Unit V µA µA ns ns
2691 tbl 06
100 100
____
____
0 tRC(2)
____
____
NOTES: 1 . VCC = 2V, TA = +25°C, and is not production tested. 2 . tRC = Read Cycle Time 3 . This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
4.5V tCDR
4.5V tR
CE VIH
VDR VIH
2691 drw 04 ,
5 6.42
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