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Part: IDT74FCT16H501ATPA
Category:
Interface and Interconnect
Description: Fast CMOS 18-bit Registered Transceiver
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT74FCT16H501ATPA datasheet File size : 843 kB
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Datasheet text preview:
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Integrated Device Technology, Inc.
I DT54/74FCT16501AT/CT/ET IDT54/74FCT162501AT/CT/ET IDT54/74FCT162H501AT/CT/ET
CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type · Common features: flip-flops to allow data flow in transparent, latched and clocked 0.5 MICRON CMOS Technology modes. Data flow in each direction is controlled by output High-speed, low-power CMOS replacement for enable (OEAB and OEBA), latch enable (LEAB and LEBA) ABT functions and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; a HIGH or LOW logic level. If LEAB is LOW, the A bus data > 200V using machine model (C = 200pF, R = 0) is stored in the latch/flip-flop on the LOW-to-HIGH transition of Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack CLKAB. OEAB is the output enable for the B port. Data flow from the B port to the A port is similar but requires using OEBA, Extended commercial range of -40°C to +85°C LEBA and CLKBA. Flow-through organization of signal pins · Features for FCT16501AT/CT/ET: simplifies layout. All inputs are designed with hysteresis for High drive outputs (-32mA IOH, 64mA IOL) improved noise margin. Power off disable outputs permit "live insertion" The FCT16501AT/CT/ET are ideally suited for driving Typical VOLP (Output Ground Bounce) < 1.0V at high-capacitance loads and low-impedance backplanes. The VCC = 5V, TA = 25°C output buffers are designed with power off disable capability · Features for FCT162501AT/CT/ET: to allow "live insertion" of boards when used as backplane Balanced Output Drivers: ±24mA (commercial), drivers. ±16mA (military) The FCT162501AT/CT/ET have balanced output drive Reduced system switching noise with current limiting resistors. This offers low ground bounce, Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall timesreducing VCC = 5V,TA = 25°C the need for external series terminating resistors. The · Features for FCT162H501AT/CT/ET: FCT162501AT/CT/ET are plug-in replacements for the Bus Hold retains last active bus state during 3-state FCT16501AT/CT/ET and ABT16501 for on-board bus inter Eliminates the need for external pull up resistors face applications. The FCT162H501AT/CT/ET have "Bus Hold" which reDESCRIPTION: tains the input's last state whenever the input goes to high The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18- impedance. This prevents "floating" inputs and eliminates the bit registered transceivers are built using advanced dual metal need for pull-up/down resistors.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKBA LEBA OEBA CLKAB LEAB C A1 D C B1 D
C D
C D
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2547/8
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND CLKAB B1 GND B2 B3 V CC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 V CC B16 B17 GND B18 CLKBA GND
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OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
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GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND
SSOP/ TSSOP/TVSOP TOP VIEW
CERPACK TOP VIEW
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names OEAB Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs
(1) (1)
FUNCTION TABLE(1,4)
Inputs LEAB CLKAB X H H L L L L X X X L H Outputs Bx Z L H L H B (2) B (3)
OEBA
LEAB LEBA CLKAB CLKBA Ax Bx
OEAB L H H H H H H
Ax X L H L H X X
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTE: 2547 tbl 01 1. On FCT16xH501T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to 0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to 0.5 to GND VCC +0.5 TSTG Storage Temperature 65 to +150 I OUT DC Output Current 60 to +120 Unit V V °C mA
NOTES: 2547 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
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CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
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NOTE: 1. This parameter is measured at characterization but not tested.
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