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Part: IDT74FCT821ATD
Category:
Logic
-> Bus Interface
Description: High-performance CMOS Bus Interface Registers
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT74FCT821ATD datasheet File size : 843 kB
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Datasheet text preview:
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
Integrated Device Technology, Inc.
IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT
FEATURES:
· Common features: Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages · Features for FCT821T/FCT823T/FCT825T: A, B, C and D speed grades High drive outputs (-15mA IOH, 48mA IOL) Power off disable outputs permit "live insertion"
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high IOL/IOH. The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 EN
DN
CLR D CL Q D CL Q
CP Q
CP Q
CP
OE Y0 YN
2567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc
AUGUST 1995
DSC-4202/5
6.21 6.21
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1
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
D8 D9 GND NC CP Y9 Y8
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND
1 2 3 4 P24-1 5 D24-1 6 SO24-2 7 SO24-7 SO24-8 8 & 9 E24-1 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
D1 D0 OE NC V CC Y0 Y1
FCT821 10-BIT REGISTER
Y2 Y3 Y4 NC Y5 Y6 Y7
2567 drw 02
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
D8 CLR GND NC CP EN
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND
1 2 3 P24-1 4 D24-1 5 SO24-2 6 SO24-7 7 SO24-8 8 & 9 E24-1 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
Y8
D1 D0 OE NC VCC Y0 Y1
FCT823 9-BIT REGISTER
INDEX
Y2 Y3 Y4 NC Y5 Y6 Y7
2567 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
FCT825 8-BIT REGISTER
INDEX OE1 OE2 D0 D1 D2 D3 D4 D5 D6 D7 CLR GND 24 1 23 2 22 3 4 P24-1 21 5 D24-1 20 6 SO24-2 19 7 SO24-8 18 & 17 8 E24-1 16 9 10 15 14 11 12 13 VCC OE3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 EN CP
D0 OE2 OE1 NC VCC OE3 Y0
D1 D2 D3 NC D4 D5 D6
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
D7 CLR GND NC CP EN Y7
Y1 Y2 Y3 NC Y4 Y5 Y6
2567 drw 04
DIP/SOIC/QSOP/CERPACK TOP VIEW
6.21
LCC TOP VIEW
2
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Names DI
CLR
FUNCTION TABLE(1)
Inputs
OE CLR EN
I/O I I
Description The D flip-flop data inputs. When the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-toHIGH transition. The register 3-state outputs. Clock Enable. When the clock enable is LOW, data on the D I input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Y I outputs are in the highimpedance state. When the OE input is LOW, the TRUE register data is present at the YI outputs.
2567 tbl 01
DI L H X X X X L H L H
CP X X X X
Internal/ Outputs QI YI L H L L NC NC L H L H Z Z Z L Z NC Z Z L H
H H H L H L H H L L
H H L L H H H H H H
L L X X H H L L L L
Function High Z Clear Hold Load
CP
I
YI
EN
O I
OE
I
NOTE: 1. H = HIGH L = LOW X = Don't Care NC = No Change = LOW-to-HIGH Transition Z = High Impedance
2567 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial (2) Terminal Voltage VTERM 0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage 0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature 55 to +125 Under Bias TSTG Storage 55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current 60 to +120 Military 0.5 to +7.0 Unit V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2567 lnk 04
0.5 to VCC +0.5 55 to +125 65 to +135 65 to +150 0.5 60 to +120
V °C °C °C W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2567 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
6.21
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