|
|
Part: IDT74LVCH16701A
Category:
Logic
-> Buffers/Inverters
-> 2-State
-> CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage
Description: 3.3v CMOS 18-bit Read/write Buffer With 5v Tolerant I/o And Bus-hold
Company: Integrated Device Technology, Inc.
Datasheet: Download IDT74LVCH16701A datasheet File size : 843 kB
Request For quote: Find where to buy IDT74LVCH16701A
Datasheet text preview:
IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
· Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · CMOS power levels (0.4µ W typ. static) µ · All inputs, outputs, and I/O are 5V tolerant · Supports hot insertion · Available in SSOP, TSSOP, and TVSOP packages
IDT74LVCH16701A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
· High Output Drivers: ±24mA · Reduced system switching noise
The LVCH16701A 18-bit read/write buffer is built using advanced dual metal CMOS technology. The device is designed as an 18-bit read/write buffer with a four deep FIFO and a read-back latch. It can be used as a read/ write buffer between a CPU and a memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16701A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16701A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
A1-18
3
18
27
OEBA
RESET CLK WCE RCE FF
29 55 Q 2 56 30
FIFO (4 deep)
LATCH
D
LE
28
LE
OEAB
1
18
54
B1-18
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4233/3
IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND 0.5 to +6.5 65 to +150 50 to +50 50 ±100 TSTG IOUT IIK IOK ICC ISS
Unit V °C mA mA mA
OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE
RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1 . As applicable to the device type.
SSOP/ TSSOP/ TVSOP TOP VIEW
2
IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names A1-18 B1-18 CLK WCE RCE FF RESET OEAB OEBA LE I/O I/O I/O I I I O I I I I 18 bit I/O port (1) 18 bit I/O port (1) Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low. Enable pin for FIFO input clock (Active LOW) Enable pin for FIFO output clock (Active LOW) Write path FIFO full flag. Goes low when FIFO is full. Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset. (Active LOW) Output Enable pin for B port (Active LOW) Output Enable pin for A port (Active LOW) Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE. (Note: LE is independent of CLK and data)
NOTE: 1 . These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Description
FUNCTION TABLE(1)
Inputs OEBA H L L H H L OEAB H H H H L L LE H H L X X L RESET H H H H H H CLK Q (B) Bus Hold
(2) (2) (2) (2)
Outputs Ax Q (B) Bus Hold B to A Qo(B) Q (A) Bus Hold Q(2)(B) Bus Hold A to B - 4 CLKS Q (B) - 4 CLKS Bus Hold Case not recommended
(2)
Bx Q (A) -4CLKS Bus Hold
Notes Transparent Mode
NOTES: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2 . Level of Q before the indicated steady-state input conditions were established.
FUNCTIONAL DESCRIPTION
remains at the output of the FIFO. The FIFO may be reset by the synchronous RESET input. This resets the read and write pointers to the original "empty" condition and also sets all B outputs = 1. Simultaneous read and write attempts (clock data into FIFO as well as clock data out of FIFO) are possible except on FIFO empty and full boundaries. When the FIFO The four deep FIFO uses one clock with two clock enable pins, WCE and is empty, and a simultaneous read and write is attempted, the read is ignored RCE to clock data in and out. The FIFO has an external full flag which goes while the write is executed. If the same is attempted when the FIFO is full, LOW when the FIFO is full. Internal read and write pointers keep track of the write is ignored while the read is executed. Normal operation of the four the words stored in the FIFO. A write attempt to a full FIFO is ignored. An deep FIFO in the write path is independent of the read path operation. attempt to read from an empty FIFO will have no effect and the last read data
3
This device is useful as a read/write buffer for modular high end designs. It provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. The read path provides a transparent latch.
Others parts begin by id
ID-1 ID-2 ID-3 ID-4 ID-5 ID-6 ID-7 ID-8 ID-9 ID-10 ID-11 ID-12 ID-13 ID-14 ID-15 ID-16 ID-17 ID-18 ID-19 ID-20 ID-21 ID-22 ID-23 ID-24 ID-25 ID-26 ID-27 ID-28 ID-29 ID-30 ID-31 ID-32 ID-33 ID-34 ID-35 ID-36 ID-37 ID-38 ID-39 ID-40 ID-41 ID-42 ID-43 ID-44 ID-45 ID-46 ID-47 ID-48 ID-49 ID-50 ID-51 ID-52 ID-53 ID-54 ID-55 ID-56 ID-57 ID-58 ID-59 ID-60 ID-61 ID-62 ID-63 ID-64 ID-65 ID-66 ID-67 ID-68 ID-69 ID-70 ID-71 ID-72 ID-73 ID-74 ID-75 ID-76 ID-77 ID-78 ID-79 ID-80 ID-81 ID-82 ID-83 ID-84 ID-85 ID-86 ID-87 ID-88 ID-89 ID-90 ID-91 ID-92 ID-93 ID-94 ID-95 ID-96 ID-97 ID-98 ID-99 ID-100 ID-101 ID-102 ID-103 ID-104 ID-105 ID-106 ID-107 ID-108 ID-109 ID-110 ID-111 ID-112 ID-113 ID-114 ID-115 ID-116 ID-117 ID-118 ID-119 ID-120 ID-121 ID-122 ID-123 ID-124 ID-125 ID-126 ID-127 ID-128 ID-129 ID-130 ID-131 ID-132 ID-133 ID-134 ID-135 ID-136 ID-137 ID-138 ID-139 ID-140 ID-141 ID-142
|
|
|
