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Details, datasheet, quote on part number:QS59920
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Datasheet text preview:
IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW PLL CLOCK DRIVER TURBOCLOCKTM JR.
FEATURES:
· · · · · · Eight zero delay outputs Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 25MHz to 85MHz CMOS outputs 3 skew grades: QS59920 -2: tSKEW0 <250ps QS59920 -5: tSKEW0 <500ps QS59920 -7: tSKEW0 <750ps 3-level input for PLL range control PLL bypass for DC testing External feedback, internal loop filter 46mA IOL high drive outputs Low Jitter: <200ps peak-to-peak Outputs drive 50 terminated lines Pin compatible with Cypress CY7B9920 Available in SOIC Package
QS59920
DESCRIPTION:
The QS59920 is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The QS59920 has CMOS outputs. The QS59920 maintains Cypress CY7B9920 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/ sOE pin is held low, all outputs are synchronously enabled (CY7B9920 compatibility). However, if GND/sOE is held high, all outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all outputs are synchronized with the positive edge of the REF clock input (CY7B9920 compatibility). When VDDQ/PE is held low, all outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
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FUNCTIONAL BLOCK DIAGRAM
V D D Q /P E G N D /s O E Q0 Q1
Q2 Q3 P LL REF Q4 Q5 FS Q6 Q7
FB
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c 1999 Integrated Device Technology, Inc.
MARCH 2000
DSC-5813/-
IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Supply Voltage to Ground DC Input Voltage Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature Range Max. 0.5 to +7 0.5 to +7 530
(1)
Unit V V mW
REF V DD Q FS NC V D D Q /P E V D DN Q0 Q1 GND Q2 Q3 V D DN
1 2 3 4 5 6 7 8 9 10 11 12 S O 2 4 -2
24 23 22 21 20 19 18 17 16 15 14 13
GND TE ST NC G N D /s O E V DDN Q7 Q6 GND Q5 Q4 V DDN FB
VI
65° C to +150°C ° C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. Max. 5 7 Unit pF
SOIC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE (1) VDDQ/PE FS (2) Type IN IN IN IN IN IN Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Frequency range select. 3 level input. FS = GND: 25 to 35MHz. FS = MID (or open): 35 to 60MHz FS = VDD: 60 to 85MHz 8 clock output Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground Description
Q0 - Q7 VDDN VDDQ GND
OUT PWR PWR PWR
NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
2
IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
QS59920-5, -7 (Industrial) Symbol VDD TA Description Power Supply Voltage Ambient Operating Temperature Min. 4.5 -40 Max. 5.5 +85 Min. 4.75 0 QS59920-2 (Commercial) Max. 5.25 +70 Unit V °C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage
(1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD or GND VDD = Max. VIN = VDD VIN = VDD/2 VIN = GND VDD = Max., VIN = GND VDD = Max., VIN = VDD VDD = Min., IOH = -16mA VDD = Min., IOH = -40mA VDD = Min., IOL = 46mA VDD = Max., VO = GND
Min. VDD-1.35 -- VDD-1 VDD/2-0.5 -- --
Max. -- 1.35 -- VDD/2+0.5 1 ±5 ± 200 ± 50 ± 200 ± 100 ± 100 -- -- 0.45 N/A
Unit V V V V V µA
Input MID Voltage (1)
(1)
Input Leakage Current (REF, FB Inputs Only) 3-Level Input DC Current (TEST, FS) Input Pull-Up Current (VDDQ/PE) Input Pull-Down Current (GND/sOE) Output HIGH Voltage Output LOW Voltage Output Short Circuit Current (2)
HIGH Level MID Level LOW Level
-- -- -- -- -- -- VDD-0.75 -- --
I3 IPU IPD VOH VOL IOS
µA µA µA V V V mA
NOTES: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. QS59920 outputs are not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD ITOT Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current Test Conditions VDD = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VDD = Max., VIN = 3.4V VDD = Max., CL = 0pF VDD = 5V, FREF = 25MHz, CL = 240pF (1) VDD = 5V, FREF = 33MHz, CL = 240pF (1) VDD = 5V, FREF = 66MHz, CL = 240pF (1)
NOTE: 1. For eight outputs, each loaded with 30pF.
Typ. 10 0.4 100 53 63 117
Max. 40 1.5 160 -- -- --
Unit mA mA µA/MHz mA mA mA
3
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