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Details, datasheet, quote on part number:QS5LV919
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| Part: | QS5LV919 |
| Category: | Timing Circuits => Clock Distribution => General Purpose/ |
| Description: | 3.3v Low Skew CMOS PLL Clock Driver With Integrated Loop Filter |
| Company: | Integrated Device Technology, Inc. |
| Datasheet: | Download QS5LV919 datasheet File size : 101 kB |
| Request For quote: | Find where to buy QS5LV919
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Datasheet text preview:
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES: DESCRIPTION:
Q S 5 LV 9 1 9
· · · · · · · · · · · · ·
3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages
The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
RE F_ S E L LO C K SYNC0 SYNC1 O E /R S T
0 0 1 PH ASE D ETE C TO R LOO P F IL T E R 1
PE
FE E DB A CK
P LL _ E N
FR E Q _ S E L
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /2
Q5
Q4
Q3
Q2
Q1
Q0
2xQ
INDUSTRIAL TEMPERATURE RANGE
c 2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JULY 2001
1
DSC-5820/3
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE/RST
GND
Q5 VDD OE/RST FEEDBACK REF_SEL SYNC0 AVDD PE AGND SYNC1 FREQ_SEL GND Q0
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
VDD 2xQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD
AGND SYNC1 10 11 FEEDBACK REF_SEL SYNC0 AVDD PE 5 6 7 8 9
4
3
2
1
28
27
26 25 24 23 22 21 20 19 Q/2 GND Q3 VDD Q2 GND LOCK
12
FREQ_SEL
13
GND
14
Q0
15
VDD
16
Q1
17
GND
18
PLL_EN
QSOP TOP VIEW
PLCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating DC Input Voltage VIN Maximum Power TSTG QSOP Dissipation (TA = 85°C) P L C C Storage Temperature Range Max. 0.5 to +7 0.5 to +5.5 655 770 65 to +150 Unit V V mW mW °C VDD, AVDD Supply Voltage to Ground
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25°C, f = 1MHz, VIN = 0V)
QSOP Parameter CI N Typ. 3 Max. 4 Typ. 4 PLCC Max. 6 Unit pF
2
2xQ
VDD
Q5
Q4
VDD
GND
1
28
Q4
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name SYNC0 SYNC1 REF_SEL FREQ_SEL FEEDBACK Q0 -Q4 Q5 2xQ Q/2 LOCK OE/ R S T PLL_EN PE VDD AVDD GND AGND I/O I I I I I O O O O O I I I -- -- -- -- Description Reference clock input Reference clock input Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in frequency, but inverted with respect to Q. Clock output. Matched in phase, but frequency is double the Q frequency. Clock output. Matched in phase, but frequency is half the Q frequency. PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Useful for testing purposes. When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. Power supply for output buffers. Power supply for phase lock loop and other internal circuitries. Ground supply for output buffers. Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = 40°C to +85°C, AVDD / VDD = 3.3V ± 0.3V
Symbol FMAX_2XQ FMAX_Q FMAX_Q/2 FMIN_2XQ FMIN_Q FMIN_Q/2 Description Max Frequency, 2xQ Max Frequency, Q0 - Q4, Q5 Max Frequency, Q/2 Min Frequency, 2xQ Min Frequency, Q0 - Q4, Q5 Min Frequency, Q/2 55 55 27.5 13.75 20 10 5 70 70 35 17.5 20 10 5 100 100 50 25 20 10 5 133 133 66.5 33.25 20 10 5 160 160 80 40 20 10 5 Units MHz MHz MHz MHz MHz MHz
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