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Details, datasheet, quote on part number:QS5LV931
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| Part: | QS5LV931 |
| Category: | Timing Circuits => Clock Distribution => General Purpose/ |
| Description: | 3.3v Low Skew CMOS PLL Clock Driver With Integrated Loop Filter |
| Company: | Integrated Device Technology, Inc. |
| Datasheet: | Download QS5LV931 datasheet File size : 64 kB |
| Request For quote: | Find where to buy QS5LV931
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Datasheet text preview:
QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES: DESCRIPTION:
Q S 5 LV 9 3 1
· · · · · · · · · · · · ·
3.3V operation JEDEC LVTTL compatible level Clock input is 5V tolerant Q outputs, Q/2 output 2000V 80MHz maximum frequency Available in QSOP package
The QS5LV931 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0Q4, Q/2. Careful layout and design ensure <300ps skew between the Q0Q4, and Q/2 outputs. The QS5LV931 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5LV931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5LV931 clock driver represents the best value in small form factor, high-performance clock management products. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
FE ED BA C K
PLL_E N
FR E Q _S EL
S Y NC O E /R S T
PH ASE D E TE C TO R LO O P F IL T E R
0
1
V CO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q /2
Q4
Q3
Q2
Q1
Q0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2002 Integrated Device Technology, Inc.
JANUARY 2002
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DSC-5821/2
QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description DC Input Voltage VIN Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature Range Max 0.5 to +7 0.5 to +5.5 0.5 65 to +150 Unit V V W °C AVDD/VDD Supply Voltage to Ground
GND OE/RST FEEDBACK AVDD VDD AGND SYNC FREQ_SEL GND Q1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Q4 Q/2 GND Q3 VDD Q2 GND PLL_EN GND Q1
NOTE: 1 . Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)
Pins CI N COUT Typ. 3 4 Max. 4 5 Unit pF pF
QSOP TOP VIEW
PIN DESCRIPTION
Pin Name SYNC FREQ_SEL FEEDBACK Q0 -Q4 Q/2 OE/ R S T PLL_EN VDD AVDD GND AGND I/O I I I O O I I -- -- -- -- Description Reference clock input VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies, LOW is for lower frequencies. PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in phase, but frequency is half the Q frequency. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug. Power supply for output buffers Power supply for phase lock loop and other internal circuitries Ground supply for output buffers Ground supply for phase lock loop and other internal circuitries
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = 40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V
Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Max Frequency, Q0 - Q4, Max Frequency, Q/2 Min Frequency, Q0 - Q4 Min Frequency, Q/2 50 50 25 10 5 66 66 33 10 5 80 80 40 10 5 Units MHz MHz MHz MHz
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QS5LV931 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz) Output Used for FREQ_SEL HIGH HIGH LOW LOW Feedback Q/2 Q0 -Q4 Q/2 Q0 -Q4 Min. FMIN_Q/2 FMIN_Q FMIN_Q/2 /2 FMIN_Q /2 (allowable range) (1) Max FMAX _Q/2 FMAX _Q FMAX _Q/2 /2 FMAX _Q /2 Output Frequency Relationships Q/2 SYNC SYNC / 2 SYNC SYNC / 2 Q0 - Q4 SYNC X 2 SYNC SYNC X 2 SYNC
NOTE: 1 . Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_Q x2. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V
Symbol VIH VIL VOH VOL VH IOZ IIN Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Hysteresis Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level IOH = -24mA IOH = -100µA VDD = Min., IOL = 100µA -- VOUT = VDD or GND, VDD = Max., Outputs Disabled AVDD = Max., VIN = AVDD or GND -- -- 5 µA Min. 2 -- VDD -- 0.6 VDD -- 0.2 -- -- -- -- Typ. -- -- -- -- -- -- 100 -- Max. -- 0.8 -- -- 0.45 0.2 -- 5 mV µA V Unit V V V
VDD = Min., IOL = 24mA
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3V VDD = Max., CL = 0pF 1 0.2 30 0.3 µA µA/MHz Typ. -- Max. 1 Unit mA
INPUT TIMING REQUIREMENTS
Symbol tR, tF FI tPWC DH Input Clock Frequency, SYNC Duty Cycle, SYNC
(2) (1)
Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW (2)
Min. -- 2.5 2 25
Max. 3 FMAX _Q -- 75
Unit ns MHz ns %
NOTES: 1 . See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2 . Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
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