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Details, datasheet, quote on part number:QS5V991
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| Part: | QS5V991 |
| Category: | Timing Circuits => Clock Distribution => General Purpose/ |
| Description: | 3.3v Programmable Skew PLL Clock Driver Turboclock(tm) |
| Company: | Integrated Device Technology, Inc. |
| Datasheet: | Download QS5V991 datasheet File size : 125 kB |
| Request For quote: | Find where to buy QS5V991
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Datasheet text preview:
QS5V991 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM
FEATURES/BENEFITS
· · · · · · · · REF is 5V tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 6.25MHz to 85MHz 2x, 4x, 1/2, and 1/4 outputs 3 skew grades: Q S 5 V 9 9 1 - 2 : tS K E W 0 < 2 5 0 p s Q S 5 V 9 9 1 - 5 : tS K E W 0 < 5 0 0 p s Q S 5 V 9 9 1 - 7 : tS K E W 0 < 7 5 0 p s 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <200ps peak-to-peak Industrial temperature range Available in 32-pin PLCC Package
QS5V991
DESCRIPTION
The QS5V991 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The QS5V991 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
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FUNCTIONAL BLOCK DIAGRAM
G N D /s O E
S ke w S e le c t 3 3 1 F 1 :0 V C C Q /P E S ke w S e le c t REF PLL FB 3 FS S ke w S e le c t 3 3 3 F 1 :0 3 3 2 F 1 :0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
S ke w S e le c t 3 3 4 F 1 :0
4Q0 4Q1
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c 2000 Integrated Device Technology, Inc.
MARCH 2000
DSC-5786/-
QS5V991 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
3F0 TE S T VC CQ G ND REF 2F1 FS
ABSOLUTE MAXIMUM RATINGS
Symbol VI
29 28 27 26 2F0 G N D /s O E 1F1 1F0 VCC N 1Q0 1Q1 G ND G ND
(1)
Unit V V V W
Rating Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power Dissipation (TA = 85°C)
Max. 0.5 to +7 0.5 to VCC+0.5 0.5 to +5.5 0.8
4 3F1 4F0 4F1 V CC Q /P E VCC N 4Q1 4Q0 G ND G ND 5 6 7 8 9 10 11 12 13 14
3
2
1
32
31
30
TSTG
Storage Temperature Range
65° C to +150°C ° C
J3 2 -1
25 24 23 22 21
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. 7 Unit pF
VC CN
VC CN
3Q0
3Q1
FB
2Q1
2Q0
LCC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE (1) Type IN IN IN IN Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control Summary Table) remain in effect. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) Four banks of two outputs with programmable skew Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground Description
VCCQ/PE nF[1:0] FS nQ[1:0] VCCN VCCQ GND
IN IN IN OUT PWR PWR PWR
NOTE: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see PLL Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order 2 to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins.
QS5V991 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the QS5V991 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM) (1,2) Skew Adjustment Range (3) Max Adjustment: ± 9.09ns ± 49º ± 14% Example 1, FNOM = 25MHz Example 2, FNOM = 30MHz Example 3, FNOM = 40MHz Example 4, FNOM = 50MHz Example 5, FNOM = 80MHz tU = 0.91ns tU = 0.76ns -- -- -- ± 9.23ns ± 83º ± 23% -- -- tU = 0.96ns tU = 0.77ns -- ± 9.38ns ± 135º ± 37% -- -- -- -- tU = 0.78ns ns Phase Degrees % of Cycle Time 1/(44 x FNOM) 25 to 35MHz FS = MID 1/(26 x FNOM) 35 to 60MHz FS = HIGH 1/(16 x FNOM) 60 to 85 MHz Comments
NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its `sweet spot' where jitter is lowest. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed 4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value. 4. The maximum REF Clock Input Frequency is 70MHz. Use Q/2 or Q/4 as feedback and use the Control Summary Table explicitly for output frequency to 85MHz.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0 LL (1) LM LH ML MM MH HL HM HH Skew (Pair #1, #2) 4tU 3tU 2tU 1tU Zero Skew 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 6tU 4tU 2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 6tU 4tU 2tU Zero Skew 2tU 4tU 6tU Inverted (2)
NOTES: 1. LL disables outputs if TEST = MID and GND/sOE = HIGH. 2. When pair #4 is set to HH (inverted), GND/ sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/ sOE disables pair #4 LOW when VCCQ/PE = LOW.
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